Senior RTL Digital Design Engineer - ASIC & SoC

LitePoint; North Reading (MA); On-site; USD 192,000 - 308,000; Full time

Benefits offered by this job

Discretionary bonus

Health and well-being benefits

Tuition assistance

Job summary

Teradyne's Digital ASIC Group is seeking a Senior RTL Digital Design Engineer to develop complex mixed-signal ASICs for next-generation semiconductor test systems. You will work with architects, analog designers, verification teams, and physical design to drive digital design from architecture through silicon bring-up.

You will own critical ASIC subsystems, influence technical direction, and contribute to cutting-edge products in a highly collaborative environment while mentoring junior

Qualifications

• BSEE required; MSEE or PhD desired.
• 8+ years of ASIC or digital design experience with strong expertise in Verilog/SystemVerilog RTL development.
• Proven experience designing complex digital blocks including state machines, FIFOs, high-speed datapaths, arbitration logic, and DFT-friendly architectures.
• Strong knowledge of ASIC development flows including synthesis, static timing analysis (STA), clock domain crossing (CDC), and timing closure.
• Experience integrating third-party and custom IP into large-scale SoCs or mixed-signal ASICs.
• Proficiency with scripting and automation using Python, Tcl, Make, or similar languages.
• Experience supporting verification, silicon bring-up, debugging, and root-cause analysis.
• Strong collaboration, communication, and problem-solving skills with the ability to mentor junior engineers and drive technical excellence across cross‑functional teams.

Responsibilities

• Drive digital design activities from architecture definition through silicon bring-up.
• Own critical ASIC subsystems, influence technical direction, and contribute to cutting-edge products.
• Collaborate with architects, analog designers, verification engineers, and physical design teams.
• Mentor junior engineers and drive technical excellence across cross-functional teams.

Skills

Verilog/SystemVerilog RTL

Digital design

Scripting languages

IP integration

Mentoring & collaboration

Education

BSEE

MSEE/PhD desired

Tools

Job description

Teradyne's Digital ASIC Group is seeking a Senior RTL Digital Design Engineer to develop complex mixed-signal ASICs for next-generation semiconductor test systems. You will work with architects, analog designers, verification teams, and physical design to drive digital design from architecture through silicon bring-up.

You will own critical ASIC subsystems, influence technical direction, and contribute to cutting-edge products in a highly collaborative environment while mentoring junior