Senior ASIC Physical Design Lead – Multi-Node Tapeouts

Broadcom; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Discretionary bonus

Equity grant

Annual stock awards

401(k) + company matching

ESPP

Job summary

Broadcom is seeking an experienced Physical Design engineer to lead chip implementation for satellite projects across nodes from 40nm to 7nm. You will own floorplanning, power integrity, and timing closure while coordinating with RTL and IP teams.

The role requires Cadence Innovus expertise, TCL scripting, and a strong background in tapeouts. Expect competitive salary and comprehensive benefits in the US.

Qualifications

• BS (Electrical)+ 12 years or MS (Electrical) +10 years of experience
• Multiple tapeouts experience and extensive hands-on knowledge in various tools such as Innovus, VCLP, Formality, LEC, timing closure, and Calibre.
• Cadence Innovus usage is essential.
• TCL scripting is required, and Python is a plus

Responsibilities

• Leading and implementing chips in various high-volume consumer devices to Satellite projects from ultra-low power 40nm nodes, 16nm to 7nm.
• Physical implementation of the blocks and top-level
• Floorplanning including multi-power domain, PG planning, block-shaping & clock-tree implementation
• Interfacing with internal and external teams, including Design, IPs, and Library
• Physical Verification for block and chip-level
• Static and Dynamic IR drop Analysis. Signal and Power EM checks
• Methodology & Flow development of Physical Design & Timing Closure
• Working independently with the Synthesis & STA owners and RTL design team on Physical implementation and Power-intent requirements
• Knowledge of ESD, IO padring, Analog integration, and exposure to various types of packages, including flip-chip, wlcsp is a plus.
• Knowledge of AI tools preferable

Skills

TCL scripting

Python

Education

BS (Electrical) + 12 years

MS (Electrical) +10 years

Tools

Innovus

VCLP

Formality

LEC

Calibre

Job description

Broadcom is seeking an experienced Physical Design engineer to lead chip implementation for satellite projects across nodes from 40nm to 7nm. You will own floorplanning, power integrity, and timing closure while coordinating with RTL and IP teams.

The role requires Cadence Innovus expertise, TCL scripting, and a strong background in tapeouts. Expect competitive salary and comprehensive benefits in the US.