Lead ASIC Chip Architect — Equity & Bonus, AI Tools

Broadcom Inc.; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Medical

dental and vision plans

401(K) participation including company

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

company paid holidays

paid sick leave and vacation time

Paid Family Leave and other leaves of

Job summary

Broadcom Inc. in San Jose, CA seeks a senior Physical Design Engineer to lead chip implementations across 40nm to 7nm nodes. You will perform floorplanning, clock-tree synthesis, and power integrity checks while coordinating with RTL, IP, and library teams to ensure robust design.

Responsibilities include IR drop analysis, ESD/padring considerations, and timing-closure methodologies. Proficiency with Innovus, Calibre, TCL scripting, and Python is preferred.

Qualifications

• BS in Electrical Engineering with 12+ years of hands-on experience
• MS in Electrical Engineering with 10+ years of experience
• Multiple tapeouts experience
• Extensive hands-on knowledge in Innovus, VCLP, Formality, LEC, timing closure, and Calibre
• Cadence Innovus usage is essential
• TCL scripting is required, Python is a plus

Responsibilities

• Leading and implementing chips in various high-volume consumer devices to Satellite projects from ultra-low power 40nm nodes, 16nm to 7nm
• Physical implementation of the blocks and top-level
• Floorplanning including multi-power domain, PG planning, block-shaping & clock-tree implementation
• Interfacing with internal and external teams, including Design, IPs, and Library Physical Verification for block and chip-level
• Static and Dynamic IR drop Analysis
• Signal and Power EM checks
• Methodology & Flow development of Physical Design & Timing Closure
• Working independently with the Synthesis & STA owners and RTL design team on Physical implementation and Power‑intent requirements
• Knowledge of ESD, IO padring, Analog integration, and exposure to various types of packages, including flip‑chip, wlcsp is a plus
• Knowledge of AI tools preferable

Skills

Tapeouts experience

Power integrity analysis

TCL scripting

Python

Education

BS in Electrical Engineering

MS in Electrical Engineering

Tools

Innovus

VCLP

Formality

LEC

Calibre

Cadence Innovus

Job description

Broadcom Inc. in San Jose, CA seeks a senior Physical Design Engineer to lead chip implementations across 40nm to 7nm nodes. You will perform floorplanning, clock-tree synthesis, and power integrity checks while coordinating with RTL, IP, and library teams to ensure robust design.

Responsibilities include IR drop analysis, ESD/padring considerations, and timing-closure methodologies. Proficiency with Innovus, Calibre, TCL scripting, and Python is preferred.