Senior ASIC Physical Design Engineer — Tapeout Lead

Amazon; Cupertino (CA); On-site; USD 213,000 - 288,000; Full time

Job summary

Amazon in Cupertino, CA is seeking an ASIC Physical Design Engineer to lead full chip floorplanning, placement and tapeout, and to drive physical verification and integration for AWS Inferentia/Trainium workloads.

You will collaborate across FE, layout and foundries, mentor juniors, and tackle DRC/LVS/PERC verification while advancing next‑generation processes (5nm or below). This is a full‑time role with a competitive salary and comprehensive benefits.

Qualifications

• BS + 10yrs or MS + 7yrs in EE/CS, or related field.
• 5+ years in physical verification for advanced technology nodes.
• Design Flow Knowledge: Understanding of backend physical design flows for chip-top/subsystems (FC/Innovus)
• Expert knowledge of industry-standard physical verification tools (Calibre, IC Validator, PVS)
• Strong understanding of semiconductor manufacturing processes and design rules
• Proven track record of successful tape-outs
• Strong communication and collaboration abilities

Responsibilities

• Drive full chip floorplan, placement, integration, PV signoff and tapeout
• Collaborate with FE team to understand RTL and drive physical aspects early in design cycle
• Define, execute and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools (FC, Calibre, IC Validator)
• Perform DRC (Design Rule Checking), LVS (Layout vs. Schematic), PERC (Programmable Electrical Rule Check) verification
• Debug and resolve physical verification issues in collaboration with layout and design teams
• Interface with foundries for MT form, rule deck updates and violation waivers; Develop and maintain verification runsets and methodologies
• Mentor junior engineers on physical verification methodologies and closure

Skills

Scripting languages (Python, Perl, B k

Education

BS + 10yrs or MS + 7yrs in EE/CS

Job description

Amazon in Cupertino, CA is seeking an ASIC Physical Design Engineer to lead full chip floorplanning, placement and tapeout, and to drive physical verification and integration for AWS Inferentia/Trainium workloads.

You will collaborate across FE, layout and foundries, mentor juniors, and tackle DRC/LVS/PERC verification while advancing next‑generation processes (5nm or below). This is a full‑time role with a competitive salary and comprehensive benefits.