Senior DRAM Physical Design Lead

Micron; Boise (ID); On-site; USD 160,000 - 260,000; Full time

Benefits offered by this job

Benefits overview

Paid time off

Paid holidays

Job summary

Micron Technology is seeking a Principal Physical Design Engineer to provide technical leadership for advanced DRAM digital design implementation and signoff methodologies. You will drive physical design from RTL through tapeout, focusing on timing closure, power integrity, EMIR analysis, and design reliability across memory products.

You will collaborate across architecture, RTL, implementation, CAD, and technology teams, develop scalable physical design solutions to meet PPA targets, mentor

Qualifications

• Master's or Bachelor's with extensive ASIC physical design experience and strong STA, SI/PI, and design signoff.
• Experience with floorplanning, place & route, clock tree synthesis, and timing closure.
• Experience with industry tools and scripting for automation.

Responsibilities

• Lead physical design implementation of complex DRAM digital designs and tapeout.
• Drive power integrity strategies and signoff methodologies including EMIR and IR drop.
• Collaborate with architecture, RTL, CAD, and technology teams to resolve timing/congestion issues.
• Develop methodology improvements, automation, and provide technical leadership.
• Mentor engineers and influence future memory product roadmaps.

Skills

Python scripting

Tcl scripting

Automation

Education

Master's degree in Electrical Engineering or equivalent

Bachelor's degree with 10+ years of ASIC physical design experience

Tools

ICC2

Fusion Compiler

PrimeTime

PrimePower

RedHawk

Job description

Micron Technology is seeking a Principal Physical Design Engineer to provide technical leadership for advanced DRAM digital design implementation and signoff methodologies. You will drive physical design from RTL through tapeout, focusing on timing closure, power integrity, EMIR analysis, and design reliability across memory products.

You will collaborate across architecture, RTL, implementation, CAD, and technology teams, develop scalable physical design solutions to meet PPA targets, mentor