Senior ASIC Physical Design Engineer – Tapeout Lead

Annapurna Labs; San Diego (CA); On-site; USD 185,000 - 288,000; Full time

Job summary

Annapurna Labs designs silicon and software that accelerate innovation for cloud solutions, including custom SoCs and accelerators used in AWS data centers. We seek an ASIC Physical Design Engineer to lead chip floorplanning, placement, PV signoff, and tapeout, working with FE RTL teams and foundries to ensure high-quality implementations.

Responsibilities include optimizing verification flows, DV/DTM checks, and mentoring junior engineers, while leveraging industry tools like FC, Innovus,

Qualifications

• B.S. + 10 yrs or M.S. + 7 yrs in EE/CS or related field.
• 5+ years in physical verification for advanced technology nodes.
• Design Flow Knowledge: backend physical design flows (FC/Innovus).
• Expert knowledge of Calibre, IC Validator, PVS.

Responsibilities

• Drive full chip floorplan, placement, integration, PV signoff and tapeout.
• Collaborate with FE team to understand RTL and drive physical aspects early in design cycle.
• Define, execute and optimize verification and integration methodologies using FC, Calibre, IC Validator, PVS.
• Perform DRC, LVS, PERC verification.
• Debug and resolve physical verification issues with layout and design teams.
• Interface with foundries for MT form and rule deck updates; develop verification runsets.
• Mentor junior engineers on physical verification methodologies.

Skills

Python scripting

Perl scripting

Bash scripting

PowerShell

Physical verification

Physical design flows

Tape-outs

Communication

Mentoring

Education

B.S. in EE/CS

M.S. in EE/CS

Tools

Calibre

IC Validator

PVS

FC

Innovus

Job description

Annapurna Labs designs silicon and software that accelerate innovation for cloud solutions, including custom SoCs and accelerators used in AWS data centers. We seek an ASIC Physical Design Engineer to lead chip floorplanning, placement, PV signoff, and tapeout, working with FE RTL teams and foundries to ensure high-quality implementations.

Responsibilities include optimizing verification flows, DV/DTM checks, and mentoring junior engineers, while leveraging industry tools like FC, Innovus,