Senior ASIC Physical Verification Engineer

Annapurna Labs; San Diego (CA); In loco; USD 185.000 - 288.000; Tempo pieno

Vantaggi offerti da questo lavoro

health insurance

401(k) matching

paid time off

parental leave

Descrizione del lavoro

Annapurna Labs (U.S.) Inc. is seeking an ASIC Physical Design Integration and Verification Engineer to drive full-chip floorplanning, integration, and physical verification.

You will use Calibre, IC Validator, and PVS to ensure manufacturability and sign-off across advanced nodes, collaborating with layout and design teams and mentoring junior engineers. The role emphasizes strong problem-solving, industry-standard tool mastery, and a proactive approach to improving cloud-scale silicon in AWS

Competenze

• BS + 10yrs or MS + 7yrs in EE/CS, or related field.
• 5+ in physical verification for advanced technology nodes.
• Expert knowledge of industry-standard physical verification tools (Calibre, IC Validator, PVS).
• Strong communication and collaboration abilities.
• Design Flow Knowledge: Understanding of backend physical design flows (FC/Innovus).

Mansioni

• Drive full chip floorplan, integration and physical verification sign-off and closure.
• Define, execute and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools (Calibre, IC Validator).
• Perform DRC, LVS, PERC verification, and Fill insertion.
• Debug and resolve physical verification issues in collaboration with layout and design teams.
• Interface with foundries for MT form, rule deck updates and violation waiversDevelop and maintain verification runsets and methodologies.
• Support technology file development and qualification.
• Fine tune cloud infrastructure to improve compute and storage utilization for physical design work.
• Mentor junior engineers on physical verification methodologies and closure.

Conoscenze

Python/Perl scripting

Communication & collaboration

Backend physical design flows (FC/InNo

Formazione

BS + 10yrs or MS + 7yrs in EE/CS

Strumenti

Calibre

IC Validator

PVS

Descrizione del lavoro

Annapurna Labs (U.S.) Inc. is seeking an ASIC Physical Design Integration and Verification Engineer to drive full-chip floorplanning, integration, and physical verification.

You will use Calibre, IC Validator, and PVS to ensure manufacturability and sign-off across advanced nodes, collaborating with layout and design teams and mentoring junior engineers. The role emphasizes strong problem-solving, industry-standard tool mastery, and a proactive approach to improving cloud-scale silicon in AWS