Senior Physical Design Engineer

Google Inc.; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Bonus target 15%

Benefits

Job summary

Google is seeking a Senior Physical Design Engineer to deliver full-chip/ASIC implementation with a focus on high performance, area efficiency, and power optimization. You will own RTL2GDS and collaborate with cross-functional teams to push innovations across hardware and software boundaries.

The position requires a strong background in physical design, Verilog/SystemVerilog, and scripting, with experience in top-tier EDA tools. In-person interviews are often part of the process.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 8 years of physical design experience.
• Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
• Experience in high performance synthesis, PnR, sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for high Power, Performance, and Area (PPA) designs.
• Define and implement innovative schemes to improve Performance and Power.
• Work with cross functional teams to deliver best Quality of results.

Skills

ASIC design knowledge

Verilog/SystemVerilog

Scripting (Tcl/Perl)

Education

Bachelor's degree in Electrical Engineering

Tools

Genus

Innovus

DC

ICC

Job description

Senior Physical Design Engineer, FullChip/ASIC Implementation

Share Senior Physical Design Engineer, FullChip/ASIC Implementation

corporate_fare Google place Mountain View, CA, USA

X In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 8 years of physical design experience
• Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
• Experience in high performance synthesis, PnR, sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.

Preferred qualifications:

• Experience in top-level floorplanning, block integration.
• Experience in low power design Implementation including UPF/CPF, multi-voltage domains, power gating.
• Experience with ASIC design flows and methodology of Physical design.
• Knowledge of fundamentals of computer architecture and of Verilog/SystemVerilog.
• Understanding of Circuit design, device physics and deep submicron technology.
• Exceptional skills with scripting languages such as Tcl, or Perl.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google .

• Develop all aspects of ASIC Register Transfer Level to Graphic Data System (RTL2GDS) implementation for high Power, Performance, and Area (PPA) designs.
• Define and implement innovative schemes to improve Performance and Power.
• Work with cross functional teams to deliver best Quality of results.

Google is proud to be an equal opportunity and affirmative action employer.

We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law.

See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.