Senior ASIC Performance Architect & Modeling Lead

Meta; Baton Rouge (LA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta's Silicon Engineering organization is seeking an experienced ASIC Engineer specializing in performance and modeling to drive architectural performance analysis for custom infrastructure silicon. You will collaborate with architecture, design, and software teams to hit hyperscale throughput, latency, and efficiency targets.

You will develop cycle-accurate and transaction-level models in C++/SystemC, validate workloads pre-silicon, and mentor others in modeling techniques while shaping

Qualifications

• Requires degree in computer science/engineering or equivalent practical experience.
• 8+ years in ASIC design/silicon engineering; 5+ years in performance modeling/microarchitectural analysis/pre-silicon simulation.
• Proficiency in C++ and Python for modeling, automation, and tooling; SystemC experience.

Responsibilities

• Define and own the performance modeling strategy for custom infrastructure ASICs, including cycle-accurate and transaction-level simulation environments.
• Drive microarchitectural exploration across compute, memory, interconnect, and I/O to inform silicon architecture decisions.
• Develop and validate pre-silicon performance models predicting post-silicon behavior for data-center workloads.
• Develop low-level workloads and kernels for ML training and inference.
• Establish performance analysis methodologies, benchmarking frameworks, and bottleneck identification techniques.

Skills

Performance modeling

Microarchitectural analysis

C++

Python

SystemC

Data center workloads

RTL collaboration

Automation pipelines

Education

Bachelor's degree in a relevant field

Tools

SystemVerilog

VHDL

SystemC

C++

Job description

Meta's Silicon Engineering organization is seeking an experienced ASIC Engineer specializing in performance and modeling to drive architectural performance analysis for custom infrastructure silicon. You will collaborate with architecture, design, and software teams to hit hyperscale throughput, latency, and efficiency targets.

You will develop cycle-accurate and transaction-level models in C++/SystemC, validate workloads pre-silicon, and mentor others in modeling techniques while shaping