Senior ASIC Performance Modeling & Architecture Lead

Meta; Montgomery (AL); On-site; USD 178,000 - 250,000; Full time

Benefits offered by this job

Equity

Bonus potential

Comprehensive benefits

Job summary

Meta's Silicon Engineering team is developing custom ASICs to power AI and data center workloads at scale. You will own performance modeling strategy, drive architectural exploration, and align cross-functional teams to meet throughput and latency targets.

You will mentor peers, build cycle-accurate models, and help define long-term silicon roadmaps with automation and tooling emphasis.

Qualifications

• Bachelor's degree in CS/CE or equivalent required.
• 8+ years in ASIC design, silicon engineering, or related field.
• 5+ years in ASIC performance modeling and pre-silicon simulation.
• Proficient in C++ and Python for modeling and automation.
• Experience with cycle-accurate/transaction-level models using C++/SystemC.

Responsibilities

• Define and own performance modeling strategy for custom ASICs.
• Lead microarchitectural exploration across compute, memory, and I/O.
• Develop and validate pre-silicon models predicting post-silicon behavior.
• Create workloads/kernels for ML training/inference.
• Collaborate with RTL/physical design to meet performance targets.
• Partner with software teams to optimize workloads against silicon.
• Mentor engineers in modeling methods and analysis best practices.

Skills

C++

Python

SystemC

Pre-silicon modeling

Cycle-accurate sim

Microarchitectural analysis

Data center workloads

RTL collaboration

PPA-driven optimization

Automation scripting

Education

Bachelor's degree in CS/CE or related field

Tools

SystemVerilog

VHDL

SystemC

Job description

Meta's Silicon Engineering team is developing custom ASICs to power AI and data center workloads at scale. You will own performance modeling strategy, drive architectural exploration, and align cross-functional teams to meet throughput and latency targets.

You will mentor peers, build cycle-accurate models, and help define long-term silicon roadmaps with automation and tooling emphasis.