ASIC Architect: Performance Modeling & Microarchitecture

Meta; Sunnyvale (CA); On-site; USD 114,000 - 172,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta's Silicon Engineering organization is seeking an ASIC Engineer specializing in architecture, performance, and modeling to drive architectural performance analysis and pre-silicon modeling for custom ASICs powering Meta's AI and data center workloads.

You will develop cycle-accurate and transaction-level simulations, C++ models, and workloads for ML training/inference, collaborating with architecture, RTL, and software teams to meet hyperscale throughput and latency targets.

Qualifications

• Bachelor's degree or equivalent practical experience in CS/CE or related field.
• Degree must be completed prior to joining Meta.
• 2+ years of experience in ASIC design, silicon engineering, or related field.
• Proficiency in C++ and Python for simulation models and analysis.
• Experience in ASIC performance modeling and pre-silicon simulation.
• Experience with data center or AI accelerator workloads on custom silicon.
• Experience with cycle-accurate or transaction-level models using C++/SystemC.
• Experience defining microarchitectural specs and cross-functional alignment.
• Experience with assembly languages and compiler tech.

Responsibilities

• Drive microarchitectural exploration across compute, memory, interconnect, and I/O.
• Define and own performance modeling strategy for custom ASICs.
• Develop and maintain C++ models of AI chip IPs and subsystems.
• Develop workloads and kernels for ML training and inference.
• Establish benchmarking frameworks and bottleneck identification.
• Collaborate with architecture, RTL, and physical design teams.
• Co-optimize workload scheduling and firmware against silicon performance.
• Lead cross-functional reviews and communicate results to leadership.
• Define long-term performance modeling infrastructure roadmaps.
• Mentor engineers in modeling techniques and analysis.
• Identify and resolve performance gaps via root-cause analysis.

Skills

C++

Python

ASIC design

SystemC

Pre-silicon modeling

Performance analysis

Microarchitectural analysis

RTL coordination

Education

Bachelor's degree in CS/CE or equivalent

Degree must be completed prior to joining Meta

Tools

SystemVerilog

CUDA

Job description

Meta's Silicon Engineering organization is seeking an ASIC Engineer specializing in architecture, performance, and modeling to drive architectural performance analysis and pre-silicon modeling for custom ASICs powering Meta's AI and data center workloads.

You will develop cycle-accurate and transaction-level simulations, C++ models, and workloads for ML training/inference, collaborating with architecture, RTL, and software teams to meet hyperscale throughput and latency targets.