Senior ASIC Performance Architect & Modeling

Meta; Tallahassee (FL); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta's Silicon Engineering team seeks an experienced ASIC Engineer specializing in performance modeling and pre-silicon analysis. You will define performance modeling strategies, build cycle-accurate simulations, and guide architecture decisions to meet hyperscale throughput and latency targets.

You will collaborate with RTL, design, and software teams, develop workloads for ML training/inference, and mentor colleagues while driving long-term modeling roadmaps and tooling investments.

Qualifications

• Bachelor's degree or equivalent practical experience in computer science or engineering.
• 8+ years of ASIC/silicon experience in design or related field.
• 5+ years in ASIC performance modeling or pre-silicon simulation.

Responsibilities

• Define and own the performance modeling strategy for custom infrastructure ASICs.
• Drive microarchitectural exploration across compute, memory, interconnect, and I/O domains.
• Develop pre-silicon performance models predicting post-silicon behavior.

Skills

C++

Python

SystemC

Performance modeling

Microarchitectural analysis

RTL collaboration

Assembly languages

Compiler technologies

Education

Bachelor's degree in Computer Science or Computer Engineering

Equivalent practical experience

Tools

SystemVerilog

VHDL

Job description

Meta's Silicon Engineering team seeks an experienced ASIC Engineer specializing in performance modeling and pre-silicon analysis. You will define performance modeling strategies, build cycle-accurate simulations, and guide architecture decisions to meet hyperscale throughput and latency targets.

You will collaborate with RTL, design, and software teams, develop workloads for ML training/inference, and mentor colleagues while driving long-term modeling roadmaps and tooling investments.