ASIC Performance Architect & Modeling Engineer

Meta Careers; Sunnyvale, Northern (CA, KY); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Meta's Silicon Engineering organization in Sunnyvale, CA is seeking an ASIC Engineer specializing in performance architecture and modeling to define and drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration.

You will develop cycle-accurate and transaction-level simulation environments, maintain C++ models of AI chip IPs, and partner with architecture, design, and software teams to meet throughput, latency, and efficiency targets at hyperscale.

Responsibilities

• Drive microarchitectural exploration and trade-off analysis across compute, memory, interconnect, and I/O domains to inform silicon architecture decisions
• Define and own the performance modeling strategy for custom infrastructure ASICs, including development of cycle-accurate and transaction-level simulation environments
• Develop and maintain C++ models of AI chip IPs and subsystems for architecture exploration, performance analysis, and software development
• Develop low-level workloads and kernels for machine learning training and inference applications
• Establish performance analysis methodologies, benchmarking frameworks, and bottleneck identification techniques across the full ASIC pipeline
• Collaborate with architecture, RTL design, and physical design teams to translate performance requirements into implementable microarchitectural specifications

Skills

Microarchitectural exploration

Performance modeling

Cycle-accurate simulation

Transaction-level simulation

C++ modelling

ML workloads

Tools

Cycle-accurate simulators

Transaction-level simulators

C++

Job description

Meta's Silicon Engineering organization in Sunnyvale, CA is seeking an ASIC Engineer specializing in performance architecture and modeling to define and drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration.

You will develop cycle-accurate and transaction-level simulation environments, maintain C++ models of AI chip IPs, and partner with architecture, design, and software teams to meet throughput, latency, and efficiency targets at hyperscale.