Senior ASIC Architect: Performance & Modeling Lead

Meta; Austin (TX); On-site; USD 146,000 - 209,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta's Silicon Engineering organization is building custom silicon solutions that power AI and data center workloads. We are seeking an ASIC Engineer specializing in architecture, performance, and modeling to define performance modeling methodologies and long-term silicon roadmap strategy.

You will develop cycle-accurate models, collaborate across architecture, RTL, and physical design, and mentor others in modeling best practices while driving improvements from design to silicon.

Qualifications

• Bachelor's degree in CS/CE or related field or equivalent practical experience.
• 6+ years in ASIC design or silicon engineering.
• Proficiency in C++ and Python for sim/models/automation.
• 5+ years in ASIC performance modeling or pre-silicon simulation.
• Experience with data-center/AI workloads on custom silicon.
• Experience with cycle-accurate or transaction-level models (C++/SystemC).
• Experience defining microarchitectural specs across teams.
• Experience with assembly languages and compiler tech.

Responsibilities

• Drive microarchitectural exploration and trade-off analysis across compute, memory, interconnect, and I/O domains.
• Define and own the performance modeling strategy for custom infrastructure ASICs and develop cycle-accurate and transaction-level environments.
• Develop and maintain C++ models of AI chip IPs and subsystems for exploration and software development.
• Develop workloads and kernels for ML training and inference.
• Establish performance analysis methodologies, benchmarking and bottleneck techniques across the ASIC pipeline.
• Collaborate with architecture, RTL, and physical design to translate performance requirements into specs.
• Partner with software and systems teams to co-optimize workload scheduling, firmware and driver behavior.
• Lead cross-functional reviews and communicate results to engineering leadership.
• Define long-term performance modeling infrastructure roadmaps and tooling investments.
• Mentor engineers on performance modeling techniques and calibration.

Skills

C++

Python

SystemC

Performance modeling

Microarchitecture

Education

Bachelor's degree in Computer Science or related field

Tools

SystemVerilog

Simulation Environments

Job description

Meta's Silicon Engineering organization is building custom silicon solutions that power AI and data center workloads. We are seeking an ASIC Engineer specializing in architecture, performance, and modeling to define performance modeling methodologies and long-term silicon roadmap strategy.

You will develop cycle-accurate models, collaborate across architecture, RTL, and physical design, and mentor others in modeling best practices while driving improvements from design to silicon.