Senior ASIC Performance Architect & Modeling Engineer

Meta; Little Rock (AR); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is seeking an ASIC Engineer focused on performance architecture and modeling within the Silicon Engineering organization. You will define and drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration for custom ASICs powering Meta's infrastructure.

You will collaborate with architecture, RTL, and physical design teams to ensure throughput, latency, and efficiency targets are met for hyperscale workloads.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or equivalent practical experience
• 8+ years in ASIC design, silicon engineering, or related field
• 5+ years in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation
• Proficiency in C++ and Python for simulation models and tooling
• Experience developing cycle-accurate or transaction-level models using C++ and SystemC
• Experience with performance analysis of data center/AI accelerator workloads on custom silicon
• Experience defining microarchitectural specifications and cross-functional alignment
• Experience with assembly languages and compiler technologies

Responsibilities

• Define and own the performance modeling strategy for custom infrastructure ASICs
• Drive microarchitectural exploration and trade-offs across compute, memory, interconnect, and I/O
• Develop and validate pre-silicon performance models predicting post-silicon behavior
• Develop low-level workloads and kernels for ML training and inference
• Establish performance analysis methodologies, benchmarking frameworks, and bottleneck identification
• Collaborate with architecture, RTL, and physical design to translate requirements into microarchitectural specs
• Partner with software and systems teams to co-optimize workload scheduling and firmware behaviors
• Lead cross-functional reviews and communicate results to engineering leadership
• Define long-term performance modeling roadmaps including tooling and automation
• Mentor engineers on performance modeling techniques and analysis
• Identify and resolve performance gaps between modeled and measured silicon behavior

Skills

C++

Python

SystemC

Assembly

Performance modeling

ASIC design

Education

Bachelor's degree in CS/CE or equivalent

Tools

SystemVerilog

VHDL

Python

Job description

Meta is seeking an ASIC Engineer focused on performance architecture and modeling within the Silicon Engineering organization. You will define and drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration for custom ASICs powering Meta's infrastructure.

You will collaborate with architecture, RTL, and physical design teams to ensure throughput, latency, and efficiency targets are met for hyperscale workloads.