Senior ASIC Performance Architect & Modeling Lead

Meta; Des Moines (IA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta's Silicon Engineering organization is building custom silicon solutions that power Meta's AI and data center workloads at scale. As an ASIC Engineer specializing in performance and modeling, you will define and drive the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's infrastructure.

You will establish the performance modeling methodology and long-term silicon roadmap strategy, partnering with architecture,

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or equivalent practical experience.
• 8+ years in ASIC design, silicon engineering, or related technical field.
• 5+ years in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs.
• Proficiency in C++ and Python for developing simulation models and performance tools.
• Experience with SystemC or similar modeling environments.

Responsibilities

• Define and own the performance modeling strategy for custom infrastructure ASICs, including cycle-accurate and transaction-level simulation environments
• Drive microarchitectural exploration and trade-off analysis across compute, memory subsystem, interconnect, and I/O domains
• Develop and validate pre-silicon performance models that predict post-silicon behavior for data center workloads
• Develop low-level workloads and kernels for machine learning training and inference applications
• Establish performance analysis methodologies, benchmarking frameworks, and bottleneck identification techniques
• Collaborate with architecture, RTL design, and physical design teams to translate performance requirements into microarchitectural specifications
• Partner with software and systems teams to co-optimize workload scheduling, firmware, and driver behavior
• Lead cross-functional technical reviews and communicate results to engineering leadership
• Define long-term performance modeling infrastructure roadmaps, including tooling and automation
• Mentor other engineers on performance modeling techniques and methodologies
• Identify and resolve performance gaps between modeled and measured silicon behavior

Skills

C++

Python

SystemC

SystemVerilog

Assembly language

Performance modeling

Compiler technologies

Education

Bachelor's degree

Tools

SystemC

VHDL

Job description

Meta's Silicon Engineering organization is building custom silicon solutions that power Meta's AI and data center workloads at scale. As an ASIC Engineer specializing in performance and modeling, you will define and drive the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's infrastructure.

You will establish the performance modeling methodology and long-term silicon roadmap strategy, partnering with architecture,