Senior ASIC Performance Modeling Engineer for Hyperscale AI

Meta; Springfield (IL); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta's Silicon Engineering organization seeks an experienced ASIC Engineer focused on performance architecture and modeling. You will define and drive performance analysis, pre-silicon modeling, and microarchitectural exploration for custom ASICs powering Meta's AI and data center workloads.

You will collaborate with architecture, RTL, and software teams to ensure throughput, latency, and efficiency targets are met at hyperscale. Strong C++/Python, SystemC, and industry experience are required.

Qualifications

• Bachelor's degree in CS/CE or equivalent, with practical experience.
• 8+ years in ASIC design, silicon engineering, or related field.
• 5+ years in ASIC performance modeling or pre-silicon simulation.
• Proficiency in C++ and Python for modeling and automation.
• Experience with cycle-accurate or transaction-level models (C++/SystemC).
• Experience with data center, AI accelerator, or HPC workloads on custom silicon.
• Ability to define microarchitectural specifications and align cross-functional teams.
• Experience with assembly languages and compiler technologies.

Responsibilities

• Define and own the performance modeling strategy for custom infrastructure ASICs, including simulation environments.
• Drive microarchitectural exploration and trade-off analysis across compute, memory, interconnect, and I/O.
• Develop and validate pre-silicon models that predict post-silicon behavior for DC workloads.
• Develop low-level workloads and kernels for ML training and inference.
• Establish performance analysis methodologies and benchmarking frameworks.
• Collaborate with architecture, RTL, and physical design to translate requirements into specs.
• Co-optimize workload scheduling, firmware, and driver behavior against silicon performance.
• Lead cross-functional reviews and communicate results to engineering leadership.
• Define long-term performance modeling roadmaps, tooling, and automation investments.
• Mentor engineers on modeling techniques and best practices.
• Identify and resolve gaps between modeled and measured silicon behavior.

Skills

Performance modeling

C++

Python

SystemC

Microarchitectural analysis

Pre-silicon simulation

Automation frameworks

Data center workloads

Collaboration across teams

RTL/PH design collaboration

Education

Bachelor's degree in Computer Science, Computer Engineering or related field

Tools

SystemVerilog

SystemC

Job description

Meta's Silicon Engineering organization seeks an experienced ASIC Engineer focused on performance architecture and modeling. You will define and drive performance analysis, pre-silicon modeling, and microarchitectural exploration for custom ASICs powering Meta's AI and data center workloads.

You will collaborate with architecture, RTL, and software teams to ensure throughput, latency, and efficiency targets are met at hyperscale. Strong C++/Python, SystemC, and industry experience are required.