ASIC Engineer Principal

WarmStart Ltd; Sunnyvale, Northern (CA, KY); Hybrid; USD 180,000 - 260,000; Full time

Job summary

Hewlett Packard Enterprise (HPE) in Sunnyvale, CA seeks a Principal ASIC Engineer to drive physical design of SoC from RTL to GDSII in a hybrid role.

You will lead floorplanning, IP integration, clock and power networks, and work with architecture, frontend, DV and packaging teams to deliver robust tapeouts.

Qualifications

• BS or MS with 5+ years experience in SoC physical design.
• Deep design experience in large SoC designs, including IP integration and padring design.
• Extensive knowledge in Physical Design practices: synthesis, floor-planning, place & route.
• Experience in LVS/DRC/ERC/ANT issues and PD verification.

Responsibilities

• Implement physical design flow for large SoC from RTL to GDSII.
• Integrate IP blocks and sub-chips across a large SoC.
• Collaborate with packaging on Microbump and pad placement.
• Build full chip floorplan including power grid design.
• Develop chip-level clock network with clock experts.
• Budget timing and generate static timing constraints.
• Optimize feedthroughs and repeaters across blocks.
• Perform block-level place and route to meet timing.
• Generate ECOs to fix timing and SI violations.
• Incorporate DFT with test strategies.
• Run PD verification: LVS/DRC/ERC/ANT.
• Collaborate with architecture, frontend, DV and packaging.

Skills

SoC design

Physical design

RTL-to-GDSII

Padring design

Verilog timing

Scripting: Python/TCL/Perl

Education

Bachelor's in EE/CE

MS in EE/CE

Tools

EDA Tools

Job description

Job Description:

Hewlett Packard Enterprise (HPE) is seeking a Principal ASIC Engineer to join their team in a hybrid work environment. This role focuses on the physical design of System on Chip (SoC) from RTL to GDSII, contributing to the advancement of edge-to-cloud technology. HPE values diverse backgrounds and offers a culture that encourages growth and collaboration.

Responsibilities:

• Implement physical design at the large SoC chip level from RTL to GDSII, creating a design database ready for manufacturing.
• Interact with IP vendors to understand integration requirements and integrate all blocks, IPs, and sub-chips at a large SoC level.
• Collaborate with the packaging team on Microbump/Probe Bump/Bump/Pad placement.
• Build full chip floorplan, including pads/ports/bump placement, block placement and optimization, and power grid design.
• Develop chip-level clock network and clock stations in collaboration with clock experts.
• Budget timing among blocks and sub-chips, generating static timing constraints.
• Analyze and optimize feedthrough and repeaters among all blocks/sub-chips.
• Perform block-level place and route, ensuring design meets timing, area, and power constraints.
• Generate and implement ECOs to fix timing, signal integrity, and other violations.
• Integrate DFT into physical design, ensuring alignment with test strategies and manufacturing requirements.
• Run Physical Design verification flow, fixing LVS/DRC/ERC/ANT violations.
• Collaborate with architecture, frontend design, DV, and package teams for cohesive design implementation.

Qualifications:

• BS degree in electrical engineering, computer engineering, or related field with 7+ years of experience, or MS degree with 5+ years of experience.
• Deep design experience in large SoC designs, including IP integration and padring design.
• Extensive knowledge in Physical Design practices, including synthesis, floor-planning, and place & route.
• Experience in developing power-grid and clock networks at chip level.
• Knowledge of SoC architecture and HDL languages like Verilog for timing fixes.
• Experience in physical design verification to debug LVS/DRC/ERC/ANT issues.
• Experience in custom place and route.
• Exposure to 2.5D/3D packaging and DFT is preferred.
• Proficiency in writing Linux shell scripts in Perl, TCL, and Python.
• Real chip tapeout experience in 7nm and/or below with a successful signoff track record.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Work Email

Free No obligation Response within 24 hours