Senior ASIC PD Engineer — Cache Coherent Interconnects

Nvidia Corporation in; Santa Clara (CA); On-site; USD 136,000 - 265,000; Full time

Job summary

NVIDIA is seeking a Senior ASIC Physical Design Engineer to join the Cache Coherent Interconnects team in Santa Clara, CA. You will drive the physical design of the on-chip interconnects and last-level caches, focusing on synthesis, timing closure, and power/area goals while coordinating with the RTL and logic teams.

The role requires a Master's degree and 5+ years in high-performance semiconductor design, with strong Verilog, PD tools, and RTL/DFT/ECO expertise.

Qualifications

• Master's degree in Electrical/Computer Engineering or Computer Science or equivalent experience.
• 5+ years of experience in processor or other related high-performance semiconductor designs.
• Deep knowledge of high-frequency physical design, including synthesis, timing analysis, floor-planning and industry-standard tools.

Responsibilities

• Lead synthesis and timing closure for the on-chip interconnect network and last-level caches.
• Collaborate with the logic design team on micro-architecture feasibility and RTL/DFT/ECO considerations.

Skills

Synthesis experience

Timing analysis

Floorplanning

Verilog

RTL design & verification

DFT & ECO

Education

Master's Degree in Electrical/Computer Engineering or CS

Tools

Industry standard physical design tools

Job description

NVIDIA is seeking a Senior ASIC Physical Design Engineer to join the Cache Coherent Interconnects team in Santa Clara, CA. You will drive the physical design of the on-chip interconnects and last-level caches, focusing on synthesis, timing closure, and power/area goals while coordinating with the RTL and logic teams.

The role requires a Master's degree and 5+ years in high-performance semiconductor design, with strong Verilog, PD tools, and RTL/DFT/ECO expertise.