ASIC Physical Design Engineer, Cache Coherent Interconnects

NVIDIA; Santa Clara (CA); On-site; USD 136,000 - 265,000; Full time

Job summary

NVIDIA in Santa Clara, CA is seeking a skilled CPU design engineer to contribute to the physical design of the on-chip interconnect network and last-level caches, collaborating with the RTL/logic teams on micro-architecture feasibility and optimization. You will drive synthesis, timing closure, and power-performance trade-offs while evaluating interconnects and system caches for next-generation products.

This role emphasizes high-frequency design, HDL/RTL flow, and cross-functional teamwork in a

Qualifications

• Master’s Degree in ElectricalEngineering, ComputerEngineering or Computer Science or equivalent experience.
• 5+ years of experience in processor or other related high-performance semiconductor designs.
• Physical design expertise in high-frequency design, including hands-on synthesis experience, timing analysis, floor-planningand in-depth knowledge of industry standard physical design tools is required.
• Experience in interconnect/cache/core design is desirable.
• Verilog expertise is preferredas is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

Responsibilities

• As a member of our CPU team, you'll be responsible for synthesis and achieving timing, area, performance and power goals of the on-chip interconnect network and last-level caches.
• Help evaluate the physical design for next-generation Nvidia coherent interconnects and system-level caches.

Skills

Synthesis expertise

Timing closure

Floorplanning

RTL/ASIC design understanding

Communication skills

Education

Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science

Tools

Verilog

RTL design

DFT

EDA tools

Job description

NVIDIA in Santa Clara, CA is seeking a skilled CPU design engineer to contribute to the physical design of the on-chip interconnect network and last-level caches, collaborating with the RTL/logic teams on micro-architecture feasibility and optimization. You will drive synthesis, timing closure, and power-performance trade-offs while evaluating interconnects and system caches for next-generation products.

This role emphasizes high-frequency design, HDL/RTL flow, and cross-functional teamwork in a