ASIC Implementation Engineer, Static Verification

Anysilicon; Sunnyvale (CA); Hybrid; USD 140,000 - 200,000; Full time

Job summary

Meta in Sunnyvale, CA seeks an experienced ASIC Frontend Implementation Engineer to drive front-end implementation from RTL to netlist for data center applications.

The role emphasizes CDC/RDC analysis, RTL lint, DFT coverage, and collaboration with Design, DV, and Emulation teams to ensure timing and congestion are optimized.

Qualifications

• 6 years of experience with static verification tools.
• Experience with Lint, CDC, and Reset Domain crossing analysis.
• Knowledge of SoC CDC sign-off processes.

Responsibilities

• Perform flat and hierarchical CDC analysis with designers for sign-off.
• Conduct flat/hierarchical Reset Domain Crossing checks with Design and Firmware teams.
• Execute RTL lint checks and create waivers.
• Perform RTL DFT analysis to improve fault coverage.
• Run logic/physical synthesis to generate optimized netlists for timing, area, and power.
• Develop automation scripts for front-end tools (Lint, CDC, and Reset Domain Crossing).
• Collaborate with Design, DV, and Emulation teams on handoff and timing feedback.

Skills

CDC analysis

RTL lint

RDC/Reset domain crossing

SystemVerilog

HDL knowledge

Front-end ASIC flows

Automation scripting

Education

Bachelor's degree in CS/CE or equivalent

Tools

RTL synthesis tools

Timing analysis tools

Perl

Python

TCL

Make

Job description

ASIC Implementation Engineer, Static Verification

Meta, 1180 Discovery Way, Sunnyvale, CA 94089

Job Description:

Meta is seeking experienced ASIC Frontend Implementation Engineers to join our Infrastructure organization. The ideal candidates will have a strong background in front-end implementation processes, from RTL to netlist, specifically for data center applications.

Responsibilities:

• Perform Flat and Hierarchical Clock Domain Crossing (CDC) analysis and collaborate with designers for sign-off.


• Conduct Flat and Hierarchical Reset Domain Crossing checks, working with Design and Firmware teams to develop reset groups and sequences.


• Execute RTL Lint checks and collaborate with designers to create waivers.


• Perform RTL Design for Test (DFT) analysis to enhance coverage for Stuck-at faults.


• Run Logic/Physical Synthesis using advanced optimization techniques to generate optimized Gate Level Netlist for Timing, Area, and Power.


• Develop automation scripts and methodologies for all Front-End tools, including Lint, CDC, and Reset Domain Crossing.


• Collaborate with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks and provide feedback to Physical Design Engineers regarding timing and congestion.

Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.


• 6 years of experience with static verification tools.


• Experience with Lint, Clock Domain, and Reset Domain crossing analysis.


• Familiarity with SoC CDC signoff processes.


• Knowledge of SoC integration aspects such as clocking, reset, and PLL.


• Understanding of front-end ASIC flows.


• Experience with RTL design using SystemVerilog or other Hardware Description Languages (HDLs).


• Ability to communicate effectively across functional internal teams and with vendors.

Skills:

• Experience with Netlist-CDC Analysis and improving Mean Time Between Failures (MTBF).


• Proficiency in SoC Design Integration and Front-End Implementation.


• Scripting and programming skills in Perl, Python, TCL, and Make.


• Experience in developing structural rule-based checks for RTL and Netlist.


• Knowledge of timing/physical libraries and SRAM memories.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services


• Verification


• Packaging & Wafer


• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services


• Verification


• Packaging & Wafer


• Semiconductor IP

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