ASIC Design Engineer – Pixel IP Job ID- 894 Job ID- 3122

MaziCTools; United States; À distance; USD 176 000 - 312 000; Plein temps

Avantages offerts par ce poste

Medical and dental coverage

Retirement benefits

Discounted Apple products

Tuition reimbursement

Relocation assistance

Résumé du poste

Apple in Cupertino, California, is seeking an ASIC Design Engineer for the Pixel IP design team to craft high-performance, low-power pixel processing engines. You will collaborate with cross-functional teams to integrate large IP/SoC subsystems and ensure timely delivery of cutting-edge visuals.

The role emphasizes front-end RTL design using Verilog/SystemVerilog, clock-domain considerations, DFT, and close partnership with Physical Design and Verification teams to achieve timing closure and

Qualifications

• BS and 10+ years in ASIC/SoC front-end RTL design.
• Experience with SystemVerilog and Verilog for large IP/SoC.
• Familiarity with AMBA protocols and floorplanning/timing closure.
• Strong collaboration and communication skills.

Responsabilités

• Integrate large pixel-processing subsystems using SystemVerilog in a high-performance on-chip network.
• Write detailed micro-architectural specifications for pixel engines.
• Perform front-end implementation including synthesis, clock domain checks, STA, and power analysis.
• Collaborate with Physical Design for floorplanning and timing closure.
• Work with design verification and formal verification teams to debug and verify functionality.

Connaissances

Verilog / SystemVerilog

RTL design

Synthesis & STA

Low-power design

AMBA protocols

DFT integration

Python / TCL / Perl

Clock domain design

Cross-functional collaboration

Verification collaboration

Formation

Bachelor's degree in Electrical Engineering or related

Outils

Synthesis tools

STA tools

DFT tools

Description du poste

Cupertino,California,United States

Summary

Do you love creating elegant solutions to highly complex challenges? As part of our Hardware Technologies group, you’ll help design our next-generation, high-performance, power-efficient system-on-chips (SoCs). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices! In this highly visible role, you will be at the center of the Pixel IP design effort to capture and display beautiful images and video. You will collaborate with all disciplines, making a critical impact getting functional products to millions of customers quickly.

Description

As an ASIC Design Engineer in the Pixel IP design team, you will work closely with many cross-functional teams (chip integration, physical design, power, logic design, and verification) to build high performance and low power pixel processing engines. Your expertise in integrating large systems-on-a-chip, low-power design techniques, and front-end implementation will enable the team to deliver high performance and low power pixel processing engines on time. In this front-end design role, your tasks will include:

• Integrate large pixel-processing subsystems using SystemVerilog, connecting to high-performance on-chip networks using virtual memory addressing, adding Design-For-Test (DFT) logic, and managing clocks, resets, and power domains.
• Writing detailed micro-architectural specifications.
• Performing front-end implementation, including logic synthesis, clock & reset domain-crossing checks, static timing analysis, power analysis, logic equivalence checking.
• Working with Physical Design teams for physical floorplanning and timing closure.
• Collaborating with cross-functional teams to explore solutions that maximize performance while minimizing power and area.
• Working closely with design verification and formal verification teams to debug and verify functionality and performance.

Minimum Qualifications

BS and a minimum of 10 years relevant industry experience

Preferred Qualifications

• Experience in IP/SoC front-end ASIC RTL digital logic design using Verilog and System Verilog.
• Industry exposure to and knowledge of ASIC/FPGA design methodology, especially logic synthesis, static timing analysis, logic equivalence checking, and working with physical design teams for floorplanning and timing closure.
• Experience with system design methodologies that contain multiple clock domains.
• Experience in low-power design issues, tools, and methodologies including UPF power intent specification highly desired.
• Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
• Industry exposure to and knowledge of ASIC/FPGA design methodology including familiarity with relevant scripting languages (Python, Perl, TCL).
• Good collaboration skills with strong written and verbal communication skills.
• Experience working cross-functionally with integration, design, and verification teams to specify, design, and debug digital systems.

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,800 and $312,200, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including:

• Comprehensive medical and dental coverage
• retirement benefits
• a range of discounted products and free services
• for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition

Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.

ASIC Design Engineer - Pixel IP Job ID- 894

ASIC Design Engineer - Pixel IP Job ID- 894 Job ID- 3122