Senior ASIC Front-End Design Lead

Apple Inc.; Sunnyvale (CA); On-site; USD 216,000 - 394,000; Full time

Benefits offered by this job

Comprehensive medical and dental

Retirement benefits

Employee stock programs

Tuition reimbursement

Bonuses or commission

Relocation

Job summary

Apple Inc. in Sunnyvale is seeking an experienced ASIC Design Engineering Lead to head a team central to the SoC IP DMA design effort.

The role blends people management with strong technical leadership across micro-architecture, RTL delivery, and debug to ensure silicon-ready quality. You will guide architectural decisions, mentor engineers, and drive automation and AI-enabled tooling while coordinating with architecture, IP integration, and verification teams.

Qualifications

• Experience in technical leadership: accountable for multi-person deliverables and setting technical direction.
• Hands-on leadership with communication across management and partners.
• Excellent project planning and execution: bottom-up scheduling and resource management.
• Solid understanding of SoC architecture and high-performance designs.

Responsibilities

• Lead a team through micro-architecture, RTL delivery, and debug.
• Provide high-level technical guidance and drive design decisions.
• Develop design infrastructure, automation, and AI-enabled workflows.
• Scope features, estimate effort, and create project schedules and resources.
• Mentor engineers and foster a collaborative, growth-oriented culture.

Skills

Front-end ASIC design

Technical leadership

People management

Communication skills

Project planning

SoC architecture

AI/ML compute

High-frequency design

Education

Bachelor's degree in EE or related field

Job description

Apple Inc. in Sunnyvale is seeking an experienced ASIC Design Engineering Lead to head a team central to the SoC IP DMA design effort.

The role blends people management with strong technical leadership across micro-architecture, RTL delivery, and debug to ensure silicon-ready quality. You will guide architectural decisions, mentor engineers, and drive automation and AI-enabled tooling while coordinating with architecture, IP integration, and verification teams.