Circuit Design Engineering Lead — High-Performance ASICs

Apple Inc.; Beaverton (OR); On-site; USD 150,000 - 278,000; Full time

Benefits offered by this job

Apple shareholder programs

Restricted stock units (RSUs)

Employee Stock Purchase Plan (ESPP)

Comprehensive medical and dental

Job summary

Apple in Santa Clara, California, seeks a Circuit Design Engineering Lead to drive high‑performance, low‑power standard cells and discuss chip‑level integration with CPU/SOC/GPU teams. You will lead a small team, plan new circuit developments, and ensure DRM/PDV compliance with foundries as you advance technology nodes.

The role emphasizes leadership, hands‑on design, and collaboration across disciplines to deliver cutting‑edge ASICs for Apple customers.

Qualifications

• Bachelor's Degree + minimum 3 years of experience.
• 3+ years in Standard cells circuit development.
• Experience leading a small team.
• Strong collaboration across multi-functional teams.
• Knowledge of standard cell layout, DRM, DRC/LVS, PDV, Virtuoso.
• Experience in scripting in Perl and/or TCL.

Responsibilities

• Drive development of high performance, low power optimized standard cells to improve design PPA.
• Drive development of optimal level shifters and retention designs for low power.
• Identify next generation ideas to improve PPA.
• Engage with CPU, SOC and GPU teams on chip level integration.
• Drive circuit QA checks & analysis and develop new methodologies.
• Work with foundries on DRM compliant layout checkers and iPDK requirements.
• Plan & drive development of new circuits & technology node enablement.
• Manage migration to new PDK, PDV of standard cells & releases.

Skills

Standard cells circuit development

Leadership & mentoring

Interpersonal skills

Standard cell layout / DRM / DRC/LVS

Tech node device behavior

Circuit robustness analysis

Perl / TCL scripting

Education

Bachelor's Degree

Tools

Virtuoso

Job description

Apple in Santa Clara, California, seeks a Circuit Design Engineering Lead to drive high‑performance, low‑power standard cells and discuss chip‑level integration with CPU/SOC/GPU teams. You will lead a small team, plan new circuit developments, and ensure DRM/PDV compliance with foundries as you advance technology nodes.

The role emphasizes leadership, hands‑on design, and collaboration across disciplines to deliver cutting‑edge ASICs for Apple customers.