Senior ASIC Design Engineer — SoC Power & IP

Apple Inc.; Cupertino, Northern (CA, KY); Hybrid; USD 185,000 - 325,000; Full time

Benefits offered by this job

Stock options

Employee stock purchase plan

Medical and dental coverage

Education reimbursement

Relocation assistance

Job summary

Apple seeks an ASIC Design Engineer in Cupertino, CA to architect power management for the SoC and to write specifications for IPs. You will design, implement, and debug complex logic and integrate IPs into the SOC, while coordinating with front end teams and software groups.

The role requires a BS with 10+ years in the industry, experience leading a team of logic designers, and strong knowledge of clock domains, system architecture, and power/clock management designs.

Qualifications

• BS and a minimum of 10 years relevant industry experience.
• Experience with managing a team of logic designers.
• Experience writing specifications and converting them to design.
• Experience with multiple clock domains and asynchronous interfaces.
• Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies.
• Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs desirable.
• Ability to communicate optimally across all internal groups.
• Familiarity with software and operating concepts a plus.

Responsibilities

• Help architect solutions for power management of the SoC
• Write microarchitecture and/or design specifications for power management and other SoC level IPs
• Design, implement, and debug complex logic designs
• Integrate complex IPs into the SOC
• Support all front end integration activities like Lint, CDC, Synthesis, and ECO
• Work with other specialists that are members of the SOC Design, SOC Design Verification, Emulation, STA, and Physical Design teams
• Collaborate with software and systems teams to ensure a high quality product

Skills

Team management

Specification writing

Multiple clock domains

Front end tools

Communication across teams

Software/OS concepts

Scripting (Perl/Python/TCL)

Education

Bachelor’s degree

Tools

Front end tools and methodologies

Job description

Apple seeks an ASIC Design Engineer in Cupertino, CA to architect power management for the SoC and to write specifications for IPs. You will design, implement, and debug complex logic and integrate IPs into the SOC, while coordinating with front end teams and software groups.

The role requires a BS with 10+ years in the industry, experience leading a team of logic designers, and strong knowledge of clock domains, system architecture, and power/clock management designs.