Senior ASIC & FPGA Design Engineer

ApTask; United States; On-site; USD 140,000 - 190,000; Full time

Job summary

ApTask in the United States is seeking a senior engineer to design and develop digital ASICs and FPGAs, including mixed-signal ASICs. You will implement designs using HDL (VHDL, Verilog, SystemVerilog) and develop verification methodologies and test benches for block and system-level verification.

You will create test plans, harnesses, and coverage models, perform timing and noise analyses, and work with cross-functional teams to drive implementation challenges to solutions.

Qualifications

• 7+ years of experience in ASIC design and implementation.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline.
• Experience with FPGA & ASIC design.
• Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog).
• Experience with Linux development environment.
• Experience with design verification and test bench development.

Responsibilities

• Design and develop digital ASICs and FPGAs, and/or mixed-signal ASICs.
• Implement designs using HDL (VHDL, Verilog, SystemVerilog).
• Develop verification methodologies and test benches for block and system-level verification.
• Create and execute test plans, develop test harnesses, and implement coverage models.
• Conduct timing analysis, noise analysis, and other signoff checks.
• Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering.

Skills

ASIC design

FPGA design

HDL programming

Linux development

Design verification

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

RTL2GDSII

EDA tools

Job description

ApTask in the United States is seeking a senior engineer to design and develop digital ASICs and FPGAs, including mixed-signal ASICs. You will implement designs using HDL (VHDL, Verilog, SystemVerilog) and develop verification methodologies and test benches for block and system-level verification.

You will create test plans, harnesses, and coverage models, perform timing and noise analyses, and work with cross-functional teams to drive implementation challenges to solutions.