Remote Senior ASIC/FPGA Designer | HDL & Verification

Varstaff Staffing; El Segundo (CA); Remote; USD 124,000 - 186,000; Part time

Job summary

Varstaff is seeking a Senior ASIC/FPGA Design Engineer for a remote, US-wide 8-month contract. You will design and implement digital ASICs and FPGAs, verify via test benches, and collaborate with systems, firmware, architecture and product engineering teams.

The role requires 7+ years in ASIC/FPGA design, a Bachelor's in Electrical or Computer Engineering, and proficiency in HDL (VHDL/Verilog/SystemVerilog).

Qualifications

• 7+ years of ASIC design and implementation experience.
• Bachelor's degree in Electrical Engineering, Computer Engineering or related field.
• FPGA and ASIC design experience.
• Proficiency in HDL (VHDL, Verilog and/or SystemVerilog).
• Design verification and test bench development experience.

Responsibilities

• Design and develop digital ASICs and FPGAs and/or mixed-signal ASICs.
• Implement designs in HDL (VHDL, Verilog and/or SystemVerilog).
• Develop verification methodologies and test benches for block- and system-level verification.
• Create and execute test plans, develop test harnesses and implement coverage models.
• Conduct timing analysis, noise analysis and other signoff checks.
• Collaborate with systems, firmware, architecture and product engineering teams.
• Support lab integration and troubleshooting.
• Resolve timing, congestion and other implementation issues.

Skills

HDL (VHDL/Verilog/SystemVerilog)

ASIC design

FPGA design

Design verification

Test benches

Timing analysis

Collaboration

Education

Bachelor's degree in Electrical or Computer Engineering

MS or PhD in Electrical/Computer Engineering

Tools

EDA tools

RTL-to-GDSII flow

Job description

Varstaff is seeking a Senior ASIC/FPGA Design Engineer for a remote, US-wide 8-month contract. You will design and implement digital ASICs and FPGAs, verify via test benches, and collaborate with systems, firmware, architecture and product engineering teams.

The role requires 7+ years in ASIC/FPGA design, a Bachelor's in Electrical or Computer Engineering, and proficiency in HDL (VHDL/Verilog/SystemVerilog).