Senior ASIC DFT Engineer – Test & Bring-Up

Meta; Austin (TX); On-site; USD 146,000 - 209,000; Full time

Benefits offered by this job

Bonus

Equity

Job summary

Meta is seeking an ASIC Engineer specializing in Design for Test (DFT) to architect testability solutions for large-scale infrastructure ASICs used in data center hardware. You will drive DFT strategies from RTL to tape-out, implement scan insertion, ATPG patterns, MBIST, and LBIST, and ensure high fault coverage across multiple models.

You will collaborate with design, physical, and validation teams to balance timing, area, and power while supporting post-silicon debugging and ATE programs.

Qualifications

• 6+ years of DFT engineering for complex ASIC/SoC designs including scan insertion
• Experience with industry-standard DFT EDA tools for scan compression, ATPG, and memory test (e.g., Tessent, Synopsys DFT Compiler, TetraMAX)
• Experience achieving high fault coverage across multiple fault models on multi-million gate designs
• Experience supporting silicon bring-up and manufacturing test, including ATE correlation and scan-based diagnosis

Responsibilities

• Define and implement comprehensive DFT architectures including scan insertion, ATPG, MBIST, LBIST, and boundary scan for large-scale infrastructure ASICs
• Develop and drive DFT methodology and flows from RTL through tape-out
• Generate, simulate, and validate ATPG test patterns for high fault coverage
• Collaborate with physical design to meet timing, area, and power constraints
• Partner with validation and manufacturing test teams to define ATE test programs
• Perform DFT sign-off including fault coverage analysis and DRC/LVS compliance
• Develop and maintain DFT scripts and automation to improve flow efficiency
• Support silicon bring-up by analyzing failure data and performing scan diagnosis
• Contribute to DFT roadmap planning and improvements to Meta's silicon test strategy
• Provide technical guidance on DFT best practices and design partitioning

Skills

DFT design

ATPG pattern generation

MBIST

LBIST

Boundary scan

Education

Bachelor's degree in Computer Science or Computer Engineering

Tools

Tessent

Synopsys DFT Compiler

TetraMAX

Job description

Meta is seeking an ASIC Engineer specializing in Design for Test (DFT) to architect testability solutions for large-scale infrastructure ASICs used in data center hardware. You will drive DFT strategies from RTL to tape-out, implement scan insertion, ATPG patterns, MBIST, and LBIST, and ensure high fault coverage across multiple models.

You will collaborate with design, physical, and validation teams to balance timing, area, and power while supporting post-silicon debugging and ATE programs.