ASIC Engineer, Design for Test

Meta; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Meta is seeking an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team. You will architect testability solutions for large-scale ASICs and drive DFT strategies from RTL to silicon bring-up.

Responsibilities include achieving high fault coverage across multiple fault models, supporting silicon bring-up and manufacturing test, and collaborating with design, physical implementation, and validation teams to deliver testable silicon at scale.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or related field.
• 6+ years of experience in DFT engineering for complex ASIC/SoC designs.
• Experience with scan insertion, ATPG, and MBIST implementations.

Responsibilities

• Architect and implement testability solutions for complex, high-performance ASICs.
• Define DFT strategies from RTL through silicon bring-up.
• Collaborate with design, physical implementation, and validation teams to ensure manufacturability and high fault coverage.

Skills

DFT engineering

ATPG pattern generation

MBIST implementation

scan insertion

ATE correlation

scripting

IEEE 1500

IEEE 1687 IJTAG

post-silicon failure analysis

yield improvement

SerDes test

chiplet designs

Education

Bachelor's degree in Computer Science or Computer Engineering

Tools

Tessent

Synopsys DFT Compiler

TetraMAX

Job description

Meta is building custom silicon to power the next generation of infrastructure and computing platforms. As an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team, you will architect and implement testability solutions for complex, high-performance ASICs deployed at scale across Meta's data center infrastructure. In this role, you will define DFT strategies from RTL through silicon bring-up, ensuring manufacturability, diagnosability, and high fault coverage across large, multi-billion gate designs. You will collaborate closely with design, physical implementation, and validation teams to deliver silicon that meets aggressive quality and time-to-market targets.

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience6+ years of experience in DFT engineering for complex ASIC or SoC designs, including scan insertion, ATPG pattern generation, and MBIST implementation
• Experience with industry-standard DFT EDA tools for scan compression, ATPG, and memory test (e.g., Tessent, Synopsys DFT Compiler, TetraMAX)
• Experience achieving high fault coverage targets across multiple fault models (stuck-at, transition delay, cell-aware) on multi-million gate designs
• Experience supporting silicon bring-up and manufacturing test, including ATE correlation and scan-based diagnosis
• Experience scripting in Tcl, Python, or Perl to develop and maintain DFT automation flows
• Familiarity with IEEE 1500, IEEE 1687 (IJTAG), or IEEE 1149.1 boundary scan standards and their application in infrastructure ASICs
• Background in post-silicon failure analysis and yield improvement using scan diagnosis and statistical defect modeling
• Experience with at-speed test methodologies including launch-on-capture and launch-on-shift for timing-critical paths
• Experience with DFT architecture for high-speed SerDes interfaces, mixed-signal IP, or hierarchical test integration in large multi-die or chiplet designs