Senior ASIC DFT Engineer: From RTL to First Silicon

Rippling, Inc.; United States; Remote; USD 200,000 - 300,000; Full time

Benefits offered by this job

Health, dental, vision

401(k) matching

Unlimited PTO

Remote-first

Job summary

Positron AI seeks a Senior ASIC DFT Engineer to own end-to-end DFT from architecture to tapeout for next-gen AI accelerators. You will implement, integrate, and verify DFT solutions in RTL and with third-party IP, collaborating with Physical Design, Verification, and Firmware teams to ensure silicon quality and yield.

The role emphasizes hands-on execution, deep understanding of scan architectures, ATPG, memory BIST, and Tessent toolchain, with strong scripting and debugging skills needed for

Qualifications

• BS/MS/PhD in Electrical Engineering or Computer Engineering.
• 8+ years ASIC development experience.
• Hands-on DFT implementation on complex SoCs.
• Deep understanding of scan architectures, ATPG, memory BIST, boundary scan, IJTAG.
• Experience with Siemens Tessent DFT solutions.
• Synthesis and gate-level verification experience.
• Strong scripting in Python, Tcl, Perl.
• Excellent RTL/netlist and silicon failure debugging.
• Ability to drive cross-functional engineering teams.

Responsibilities

• Hands-on DFT implementation end-to-end from architecture to tapeout.
• Integrate DFT IP into RTL and third-party IP.
• Collaborate with physical design and backend teams for silicon bring-up.
• Develop DFT verification plans and validate via simulation and gate-level verification.
• Lead ATPG strategies and DFx coverage targets for tapeout readiness.
• Work with RTL, synthesis, and DFT tool flows.
• Partner with teams to ensure correct, compliant, complete DFT solutions.

Skills

DFT implementation

ASIC development

ATPG

Tessent

RTL debugging

Python scripting

Cross-functional

Tapeout experience

Education

BS/MS/PhD in Electrical or Computer Engineering

Tools

Siemens Tessent

Job description

Positron AI seeks a Senior ASIC DFT Engineer to own end-to-end DFT from architecture to tapeout for next-gen AI accelerators. You will implement, integrate, and verify DFT solutions in RTL and with third-party IP, collaborating with Physical Design, Verification, and Firmware teams to ensure silicon quality and yield.

The role emphasizes hands-on execution, deep understanding of scan architectures, ATPG, memory BIST, and Tessent toolchain, with strong scripting and debugging skills needed for