DFT Design Engineer for ASIC/SoC

Hardware FYI; Dallas, Northern (TX, KY); Hybrid; USD 110,000 - 160,000; Full time

Job summary

Analog Devices, Inc., a global semiconductor leader, is seeking an experienced ASIC/SoC DFT engineer to drive DFT specifications, architecture, and implementation across product lines. The role emphasizes scalable scan patterns and early verification.

You will collaborate with cross-functional teams to push high-coverage, low-power designs, perform pre/post-silicon verification and debugging, and contribute to a fast-paced, team-oriented environment.

Qualifications

• Master's degree in EE/CE or equivalent.
• 2 years of ASIC/SoC DFT experience.
• Knowledge of DFT architecture and planning.
• Hands-on scan insertion and ATPG tool experience.
• Gate-level simulation with zero delay and SDF.

Responsibilities

• DFT specifications, architecture and implementation using state-of-the-art methodologies.
• Support various product lines for DFT insertion and for high coverage, low power, low test time scan patterns.
• Pre/Post silicon verification and debugging.
• Work independently as well as in a team.

Skills

DFT architecture

ATPG Tool experience

Perl/Python/Tcl scripting

Team-player

Strong written and verbal comms

Education

Master's degree in Electrical Engineering or Computer Engineering or similar

Tools

Tessent DFT tools

Gate-level simulation tools

IEEE 1149/JTAG

Job description

Analog Devices, Inc., a global semiconductor leader, is seeking an experienced ASIC/SoC DFT engineer to drive DFT specifications, architecture, and implementation across product lines. The role emphasizes scalable scan patterns and early verification.

You will collaborate with cross-functional teams to push high-coverage, low-power designs, perform pre/post-silicon verification and debugging, and contribute to a fast-paced, team-oriented environment.