Senior ASIC DFT STA Engineer - Timing & Validation

Cisco Systems, Inc.; San Jose (CA); On-site; USD 165,000 - 241,400; Full time

Benefits offered by this job

Medical, dental, and vision insurance

401(k) plan with matching contribution

Paid parental leave

Flexible vacation policy

Job summary

Cisco Systems, Inc. is seeking an ASIC DFT STA Engineer in San Jose, California. This role involves collaborating with teams to develop and validate timing constraints, driving the DFT process through implementation.

Ideal candidates should possess a strong background in timing constraints, FPGA design, and scripting. The position offers a competitive salary range between $165,000 to $241,400 annually, reflecting the value of skilled professionals in today’s AI-driven tech environment.

Qualifications

• Bachelors + 7 years, Masters + 4 years, or PhD + 1 year of related experience.
• Experience with RTL design, CDC/RDC, and conformal verification.
• Understanding of timing constraints and verification.

Responsibilities

• Develop timing constraints at various levels in test modes.
• Perform quality checks on timing constraints.
• Develop methodologies to streamline STA work.

Skills

Timing constraint development

RTL design experience

Scripting (Perl, TCL, Python)

Debugging and analyzing PCIE timing

Education

Bachelor's degree or higher

Tools

Synopsys TCM/Primetime

Synopsys Fusion Compiler

Tessent tools

Job description

Cisco Systems, Inc. is seeking an ASIC DFT STA Engineer in San Jose, California. This role involves collaborating with teams to develop and validate timing constraints, driving the DFT process through implementation.

Ideal candidates should possess a strong background in timing constraints, FPGA design, and scripting. The position offers a competitive salary range between $165,000 to $241,400 annually, reflecting the value of skilled professionals in today’s AI-driven tech environment.