Senior ASIC DFT Engineer – Test & Validation Focus

Cisco Systems, Inc.; San Jose (CA); On-site; USD 120,000 - 150,000; Full time

Job summary

Cisco Systems, Inc. is seeking an ASIC Implementation Engineer in San Jose, CA. This role focuses on Design-for-Test for next-generation networking chips, requiring 4+ years of relevant experience. Candidates should possess a Bachelor's or Master's degree in Electrical or Computer Engineering and expertise in Jtag protocols, BIST architectures, and DFT tools. Strong debugging skills and the ability to work collaboratively are essential. This position involves influencing design processes and ensuring quality throughout the implementation flow.

Qualifications

• 4+ years experience in ASIC Design for Test.
• Experience with Jtag protocols and BIST architectures.
• Skills in System Verilog Logic Equivalency checking.
• Debugging experience with VCS and other simulators.
• Post-silicon validation using DFT patterns.

Responsibilities

• Implement Hardware Design-for-Test features supporting ATE.
• Develop innovative DFT IP in collaboration with multi-functional teams.
• Participate in creating Hardware DFT & physical design aspects.
• Craft and debug with minimal mentorship.

Skills

ASIC Design for Test Hardware Engineering

Jtag protocols

Scan and BIST architectures

ATPG tools

Verilog design

Scripting skills: Tcl, Python/Perl

Education

Bachelor's or Master's Degree in Electrical or Computer Engineering

Tools

TestMax

Tetramax

Tessent

PrimeTime

Job description

Cisco Systems, Inc. is seeking an ASIC Implementation Engineer in San Jose, CA. This role focuses on Design-for-Test for next-generation networking chips, requiring 4+ years of relevant experience. Candidates should possess a Bachelor's or Master's degree in Electrical or Computer Engineering and expertise in Jtag protocols, BIST architectures, and DFT tools. Strong debugging skills and the ability to work collaboratively are essential. This position involves influencing design processes and ensuring quality throughout the implementation flow.