Lead ASIC DFT Architect

Accord Technologies Inc; San Jose (CA); On-site; USD 130,000 - 170,000; Full time

Job summary

Accord Technologies Inc is seeking a Lead ASIC DFT Engineer in San Jose, CA. This role involves architecting and implementing DFT solutions for complex ASIC and SoC designs, requiring strong expertise in DFT architecture, scan insertion, and post-silicon validation. The ideal candidate will have over 10 years of experience and a deep understanding of DFT fundamentals. Key responsibilities include leading DFT efforts, driving high test coverage, and supporting design teams. Excellent communication skills and hands-on expertise with major EDA tools are essential.

Qualifications

• 10+ years of hands-on experience in ASIC Design-for-Test (DFT).
• Deep expertise in DFT architecture and methodologies.
• Strong hands-on experience in developing DFT constraints and validation.

Responsibilities

• Lead DFT architecture and implementation for ASIC and SoC designs.
• Drive scan insertion and workflow for high coverage.
• Perform DFT debug and failure analysis for silicon issues.

Skills

ASIC DFT experience

DFT fundamentals

Scan architecture

ATPG

MBIST

JTAG

Boundary scan

Tools

Synopsys

Cadence

Siemens/Mentor EDA tools

Job description

Accord Technologies Inc is seeking a Lead ASIC DFT Engineer in San Jose, CA. This role involves architecting and implementing DFT solutions for complex ASIC and SoC designs, requiring strong expertise in DFT architecture, scan insertion, and post-silicon validation. The ideal candidate will have over 10 years of experience and a deep understanding of DFT fundamentals. Key responsibilities include leading DFT efforts, driving high test coverage, and supporting design teams. Excellent communication skills and hands-on expertise with major EDA tools are essential.