Senior ASIC DFT & RTL Lead Engineer

Cisco; Austin (TX); Presencial; USD 187.000 - 268.000; Jornada completa

Descripción de la vacante

Cisco Systems, Inc. in Austin seeks an experienced ASIC design engineer to define, design and verify ASIC subsystems for deployment across Cisco platforms.

You will join a multi-disciplinary engineering team to meet power, performance, and area targets while helping shape design flows and methodologies. The role emphasizes RTL and CDC/RDC expertise, sign-off of constraints, and HDL debugging, with opportunities to influence high-volume production and silicon bring-up in a global hardware

Formación

• Bachelor’s with 8+ years or related experience, or master’s with 6 + years of related experience, or PhD + 3 years of related experience
• Prior experience with RTL development skills and experiences
• Prior experience with CDC/RDC concepts and relevant design implementation
• Prior Experience on maintaining CDC/RDC flow and signing-off constraints and waivers
• Prior experience with static glitch harzads and experience on synthesis optimized gate netlists

Responsabilidades

• Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms.
• Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products.
• Design, document, and develop ASIC subsystems for release in high volume and quality.
• Help define the process, methods, and tools for design and implementation of complex developments.

Conocimientos

RTL development

CDC/RDC concepts

CDC/RDC flow & sign-offs

Static glitch hazards analysis

Educación

Bachelor’s with 8+ years related experience

Master’s with 6+ years related experience

PhD with 3 years related experience

Descripción del empleo

Cisco Systems, Inc. in Austin seeks an experienced ASIC design engineer to define, design and verify ASIC subsystems for deployment across Cisco platforms.

You will join a multi-disciplinary engineering team to meet power, performance, and area targets while helping shape design flows and methodologies. The role emphasizes RTL and CDC/RDC expertise, sign-off of constraints, and HDL debugging, with opportunities to influence high-volume production and silicon bring-up in a global hardware