Senior ASIC DFT Lead: RTL/SSN & Test Strategy

Pacer Group; San Jose (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Pacer Group seeks a motivated ASIC Engineering Technical Leader focused on Design-for-Test (DFT) for next-gen multi-hundred-Gigabit to Terabit coherent optical ASICs. You will lead DFT architecture, SSN-based test flows, and memory/logic BIST, coordinating RTL and physical-design validation.

You will develop ATPG patterns, drive post-silicon testing, and automate testing with Python/Tcl/C++. Strong Verilog/SystemVerilog and ATE experience are required.

Qualifications

• Bachelor's degree with 8+ years of related experience, or Master's with 6+ years, or PhD with 3+ years.
• Experience working with ASICs and scan insertion for DFT.
• Proven ability to evaluate RTL and physical design readiness for DFT.
• Strong knowledge of SSN, memory/logic BIST, and ATPG patterns.

Responsibilities

• Lead development of DFT solutions for next-gen ASICs from design to tapeout.
• Implement SSN-based test flows, scan insertion, and BIST architectures using Tessent.
• Generate ATPG patterns for stuck-at/transition faults and debug post-silicon failures.
• Verify DFT fabrics within Subsystems and perform RTL/physical DRC checks.
• Develop test scripts and automate processes with Python/Tcl/C++.

Skills

DFT

ASICs

SSN

scan insertion

ATPG

BIST

Verilog/SystemVerilog

Python

Tcl

C++

Education

Bachelor's degree

Master's degree

PhD

Tools

Siemens Tessent

Job description

Pacer Group seeks a motivated ASIC Engineering Technical Leader focused on Design-for-Test (DFT) for next-gen multi-hundred-Gigabit to Terabit coherent optical ASICs. You will lead DFT architecture, SSN-based test flows, and memory/logic BIST, coordinating RTL and physical-design validation.

You will develop ATPG patterns, drive post-silicon testing, and automate testing with Python/Tcl/C++. Strong Verilog/SystemVerilog and ATE experience are required.