ASIC Engineering Technical Leader

Pacer Group; San Jose (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Pacer Group seeks a motivated ASIC Engineering Technical Leader focused on Design-for-Test (DFT) for next-gen multi-hundred-Gigabit to Terabit coherent optical ASICs. You will lead DFT architecture, SSN-based test flows, and memory/logic BIST, coordinating RTL and physical-design validation.

You will develop ATPG patterns, drive post-silicon testing, and automate testing with Python/Tcl/C++. Strong Verilog/SystemVerilog and ATE experience are required.

Qualifications

• Bachelor's degree with 8+ years of related experience, or Master's with 6+ years, or PhD with 3+ years.
• Experience working with ASICs and scan insertion for DFT.
• Proven ability to evaluate RTL and physical design readiness for DFT.
• Strong knowledge of SSN, memory/logic BIST, and ATPG patterns.

Responsibilities

• Lead development of DFT solutions for next-gen ASICs from design to tapeout.
• Implement SSN-based test flows, scan insertion, and BIST architectures using Tessent.
• Generate ATPG patterns for stuck-at/transition faults and debug post-silicon failures.
• Verify DFT fabrics within Subsystems and perform RTL/physical DRC checks.
• Develop test scripts and automate processes with Python/Tcl/C++.

Skills

DFT

ASICs

SSN

scan insertion

ATPG

BIST

Verilog/SystemVerilog

Python

Tcl

C++

Education

Bachelor's degree

Master's degree

PhD

Tools

Siemens Tessent

Job description

We are seeking a motivated, proactive, and intellectually curious ASIC Engineering Technical Leader with focus in Design-for-Test. In this role, you will be leading development of DFT solutions for next-generation ASICs for multi-100G to 1.6T coherent optical communications products.

Key Responsibilities

• Lead implementation of SSN based test flow DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, using Siemens Tessent tools for RTL and gate netlist DFT implementation.
• Generate and deliver ATPG test pattern for stuck-at, transition, cell aware and path delay fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post-silicon testing and validation support
• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
• Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
• Perform simulation runs and debug for non-timing and back annotated timing (SDF) gate level simulations
• Develop test scripts, automate processes, and analyze data using programming languages such as Python, Tcl, or C++

Minimum Qualifications

• Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
• Prior experience working with ASICs
• Prior experience in scan insertion and DFT setup, integration and validation
• Prior experience implementing DFT architectures—including scan insertion, compression/decompression logic, and memory/logic BIST.

Preferred Qualifications

• 10+ years of experience working with ASICs
• 10+ years of experience in scan insertion and DFT setup, integration and validation
• 3+ years of experience in SSN
• Experience driving ASIC DFT execution from concept through tapeout
• Experience working with ATE testers and test teams
• RTL experience to understand and debugging issues pertaining to DFT
• Ability to solve complex problems including clock domain crossings
• Familiar with advanced silicon process and technology nodes for high speed and low power consumption
• Strong implementation or integration of design blocks using Verilog/System Verilog