Lead ASIC DFT Engineer — SSN/RTL, 100G–1.6T

Capgemini; San Jose (CA); On-site; USD 57,000 - 90,000; Part time

Benefits offered by this job

Medical benefits

Dental benefits

Vision benefits

Retirement benefits

Job summary

Tundra Technical Solutions in San Jose, CA is seeking an ASIC Engineering Technical Leader (Contract) to drive DFT solutions for next‑gen ASICs used in high‑speed optical products. On‑site, 5 months 21 days contract, immediate start.

You will lead SSN‑based test flows, including scan insertion, compression/decompression, and memory/logic BIST, using Tessent. Strong RTL/Timing skills and scripting in Python/Tcl/C++ are preferred.

Qualifications

• Bachelors + 8 years of related experience, or Masters + 6 years, or PhD + 3 years.
• Prior experience with ASICs.
• Prior experience in scan insertion and DFT setup, integration and validation.
• Experience implementing DFT architectures including scan insertion, compression/decompression logic, and memory/logic BIST.

Responsibilities

• Lead SSN-based test flow DFT architectures including scan insertion and memory/logic BIST.
• Generate ATPG patterns for stuck-at, transition, cell-aware and path-delay fault models.
• Drive scan-based diagnosis and post-silicon testing support.
• Evaluate design readiness for RTL and physical design Scan DRC checks.
• Integrate and verify DFT fabrics and IP within Subsystems.
• Run simulations and debug non-timing and SDF-back annotated timing.
• Develop test scripts and analyze data using Python, Tcl, or C++.

Skills

Leadership

Problem solving

Mentoring

Education

Bachelor's degree or higher in Electrical/Computer Engineering

Master's degree or PhD preferred

Tools

Siemens Tessent

Verilog/SystemVerilog

Python

Tcl

C++

Job description

Tundra Technical Solutions in San Jose, CA is seeking an ASIC Engineering Technical Leader (Contract) to drive DFT solutions for next‑gen ASICs used in high‑speed optical products. On‑site, 5 months 21 days contract, immediate start.

You will lead SSN‑based test flows, including scan insertion, compression/decompression, and memory/logic BIST, using Tessent. Strong RTL/Timing skills and scripting in Python/Tcl/C++ are preferred.