Senior ASIC DFT Engineer: Lead Test & Yield

Broadcom; Fort Collins (CO); On-site; USD 110,000 - 176,000; Full time

Benefits offered by this job

Discretionary bonus

Equity grants

401(k) matching

ESPP

Job summary

Broadcom's ASIC Product Division (APD) is seeking a DFT specialist to lead end-to-end DFT programs for advanced silicon. You will drive DFT architecture, pattern generation, and verification, coordinating with Physical Design, STA and external customers.

The role requires strong DFT, scan, BIST and ATPG expertise and hands-on debugging across multi-disciplinary teams. Responsibilities include instrumenting test vectors, ATE bring-up, silicon yield improvement, and interfacing with test

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field; 8+ years of related experience or Master’s with 6+ years.

Responsibilities

• Lead DFT programs from specification to implementation and verification in ASIC products.
• Develop and verify DFT patterns and vectors for chip test coverage.

Skills

DFT background

ATPG vector generation

Verilog testbench

Memory BIST

Scan insertion

I/O DFT

Pattern generation

Debug and yield

IEEE1149.1/1149.6

TetraMax/Fastscan

Education

Bachelor's degree in relevant field

Master's degree (optional)

Tools

DFT Compiler

Mentor TestKompress

TT Xcell/ATE tools

TetraMax

Verilog simulators

Job description

Broadcom's ASIC Product Division (APD) is seeking a DFT specialist to lead end-to-end DFT programs for advanced silicon. You will drive DFT architecture, pattern generation, and verification, coordinating with Physical Design, STA and external customers.

The role requires strong DFT, scan, BIST and ATPG expertise and hands-on debugging across multi-disciplinary teams. Responsibilities include instrumenting test vectors, ATE bring-up, silicon yield improvement, and interfacing with test