Senior DFT Engineer - Yield & Pattern Debug (Equity)

Socket.dev; San Jose (CA); On-site; USD 122,000 - 195,000; Full time

Job summary

Broadcom is seeking a DFT engineer for its San Jose R&D center to drive ATPG/MBIST pattern development, defect reduction, and yield optimization across CMOS processes. You will work closely with product and test teams to debug, analyze data, and implement DFT enhancements.

The role emphasizes cross-functional collaboration, advanced testability know-how, and the use of AI tools to automate yield insights and improve time-to-market.

Qualifications

• Deep understanding of CMOS device physics and manufacturing processes.
• Knowledge of SCAN, MBIST, and bscan in digital logic and PHY/IO contexts.
• Experience with ATPG pattern generation, verification, and coverage analysis.
• Experience with Tessent tool for scan/MBIST/bscan/IJTAG pattern generation and debug.
• Post-silicon pattern conversion, pattern bring-up and debug.
• Strong pre/post-silicon debugging and analytical problem solving.
• Proficiency with data analysis software/languages.
• Self-driven with good project management and organizational skills.

Responsibilities

• DFT Pattern post-silicon support: ATPG and MBIST DFT patterns generation, bringup and debug.
• Yield enhancement: monitor wafer sort and final test yield, drive continuous improvement for yield and cost targets.
• Root cause analysis: perform scan diagnostics, mbist and repair debug, correlate failures to metrology and tool data.
• Failure analysis: support ATPG diag and guide physical failure analysis and electrical fault isolation.
• NPI & Silicon bring-up: collaborate with Global Operations to debug test programs and establish baseline yield limits.
• Cross-functional: work with Product and Test Engineers.
• Data analytics & automation: build dashboards, wafer maps, and yield models using AI tools.

Skills

CMOS physics

Manufacturing processes

Electrical testing

Testability techniques

ATPG/Scan

Post-silicon debugging

Data analysis

Scripting

Education

Bachelor's degree + 8+ years

Master's degree + 6+ years

Tools

Mentor Tessent

Job description

Broadcom is seeking a DFT engineer for its San Jose R&D center to drive ATPG/MBIST pattern development, defect reduction, and yield optimization across CMOS processes. You will work closely with product and test teams to debug, analyze data, and implement DFT enhancements.

The role emphasizes cross-functional collaboration, advanced testability know-how, and the use of AI tools to automate yield insights and improve time-to-market.