ASIC DFT Engineer

RiseMe; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Equity grants

Annual equity awards

Competitive benefits package

Job summary

Broadcom's Development Center in San Jose seeks a senior DFT engineer to lead DFT programs from specification to production release. You will handle DFT architecture, test insertion, pattern generation, and post-silicon debugging across multiple designs, interfacing with a global team.

The role requires strong DFT background (ATPG/Scan/BIST), Verilog, and memory BIST experience, with collaboration across test, design, and reliability groups.

Qualifications

• Bachelor's degree or higher with 12+ years related experience.
• Strong DFT background including IO/Analog DFT, ATPG, Scan, BIST.
• Experience with Scan Insertion and scan compression tools (DFT Compiler, Mentor TestKompress).
• Verilog coding, testbench generation and simulation.
• Memory BIST insertion and verification on embedded memories (SRAM, CAM, eDRAM, ROM).
• IEEE1149.1/1149.6 boundary scan knowledge and practice.
• Excellent debugging, problem-solving, and communication skills.

Responsibilities

• Understand Broadcom/customer DFT feature requirements and define DFT specifications for the ASIC.
• Implement DFT including Scan, MBIST, TAP, LBIST, IO, SerDes integration.
• Pattern generation and verification at chip level; rapid bring-up at ATE and RMA support.
• Collaborate with STA/DI Engineers for test closure.
• Generate, verify, and debug Test vectors before tape release.
• Validate/debug Test vectors on ATE during silicon bring-up.
• Assist with silicon failure analysis, diagnostics, and yield improvements.
• Interface with customer, physical design, and test/Manufacturing teams globally.
• Work with IP DFT engineers and other stakeholders.
• Debug customer-returned parts on ATE.
• Innovate new DFT solutions for 3nm and beyond.
• Automate DFT and Test Vector Generation flows.

Skills

DFT

IO DFT

ATPG

Scan Insertion

BIST

Verilog

Memory BIST

IEEE1149.1

IEEE1149.6

TetraMax

Fastscan

Serdes

DDR

PCIe

CXL IOBIST

Problem Solving

Communication

Project Management

Education

Bachelor's degree

Master's degree

Tools

TetraMax

Fastscan

Job description

Job Description

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.

The candidate would be required to work on various phases of SoC DFT related activities for APD's designs – DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.

Responsibilities

• Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
• Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
• Responsibilities includes pattern generation & Verification at chip level, Rapid bring-up at ATE and RMA support
• Working closely with STA and DI Engineers design closure for test
• Generating, Verifying & Debugging Test vectors before tape release.
• Validating & Debugging Test vectors on ATE during the silicon bring up phase
• Assisting with silicon failure analysis, diagnostics & yield improvement efforts
• Interfacing with the customer, physical design and testengineering/manufacturingteams located globally
• Working closely with I/P DFT engineers & other stakeholders
• Debugging customer returned parts on the ATE
• Innovating newer DFT solutions to solve testability problems in 3nm & beyond
• Automating DFT & Test Vector Generation flows

Skills/Experience

• Bachelors and 12+ years of related experience; or Masters degree and 10+ years of related experience
• Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
• Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
• Logic BIST design and debug experience
• Well-versed in ATPG vector generation, simulation, and debugging. (TetraMax, Fastscan)
• Experience in Verilog coding, testbench generation & simulation
• Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)
• Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6
• BasicknowledgeTest-STAand constraints
• Strong background on IEE1687, IJTAG, ICL and PDL
• The ability to work in a multi-disciplined, cross-department environment
• Solid knowledge in analog and digital circuit design, and device physics fundamentals
• Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
• Excellent problem solving, debug, root cause analysis and communication skills
• Strong understanding of statistical process control and data analysis techniques to drive silicon yield improvements and quality metrics
• Project management capabilities to track and prioritize competing deliverables across cross-functional stakeholders including Test Engineering, Reliability, and Operations.
• Experience working on ATE is a plus
• Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug is a plus
• Experience working on Tessent SSN is a plus

Compensation and Benefits

The annual base salary range for this position is To

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.