Senior ASIC DFT Engineer: Lead Subsystem DFT & Debug

Google; Mountain View (CA); On-site; USD 163,000 - 237,000; Full time

Job summary

Google is seeking a Senior ASIC DFT Engineer, Silicon, to lead DFT architecture across SoCs, collaborating with RTL, Physical Design, and Product teams.

The role requires 8+ years in DFT, experience with Tessent, Genus, Fusion Compiler, Simvision, and scripting in Python or Perl to automate flows. You will drive scan implementation, MBIST, ATPG, and IJTAG tooling.

This is a hands-on role with end-to-end DFT from architecture to silicon debug within Google's innovative hardware team.

Qualifications

• Requires 8 years of experience with DFT.
• Experience with DFT EDA tools (e.g., Tessent, Genus, Fusion Compiler, Simvision).
• Experience with scan insertion, ATPG, GLS debug, BIST, JTAG/IJTAG.
• Proficiency in scripting (Perl or Python).

Responsibilities

• Collaborate with multi-disciplinary teams (RTL, Physical Designers, SOC DFT, Product Eng).
• Develop tests for production in automated test equipment (ATE) and automate DFT flows.
• Drive scan implementation and verification across fault models.
• Manage GLS verification, tape-out signoff, pattern delivery, and post-silicon bring-up and debug.

Skills

DFT expertise

Scripting: Python/Perl

Education

Bachelor's degree in EE or related field

Master’s/PhD preferred

Tools

Tessent

Genus

Fusion Compiler

Simvision

Spyglass-DFT

IJTAG tools

Job description

Google is seeking a Senior ASIC DFT Engineer, Silicon, to lead DFT architecture across SoCs, collaborating with RTL, Physical Design, and Product teams.

The role requires 8+ years in DFT, experience with Tessent, Genus, Fusion Compiler, Simvision, and scripting in Python or Perl to automate flows. You will drive scan implementation, MBIST, ATPG, and IJTAG tooling.

This is a hands-on role with end-to-end DFT from architecture to silicon debug within Google's innovative hardware team.