Senior ASIC DFT Engineer, Silicon

Google; Mountain View (CA); On-site; USD 163,000 - 237,000; Full time

Job summary

Google is seeking a Senior ASIC DFT Engineer, Silicon, to lead DFT architecture across SoCs, collaborating with RTL, Physical Design, and Product teams.

The role requires 8+ years in DFT, experience with Tessent, Genus, Fusion Compiler, Simvision, and scripting in Python or Perl to automate flows. You will drive scan implementation, MBIST, ATPG, and IJTAG tooling.

This is a hands-on role with end-to-end DFT from architecture to silicon debug within Google's innovative hardware team.

Qualifications

• Requires 8 years of experience with DFT.
• Experience with DFT EDA tools (e.g., Tessent, Genus, Fusion Compiler, Simvision).
• Experience with scan insertion, ATPG, GLS debug, BIST, JTAG/IJTAG.
• Proficiency in scripting (Perl or Python).

Responsibilities

• Collaborate with multi-disciplinary teams (RTL, Physical Designers, SOC DFT, Product Eng).
• Develop tests for production in automated test equipment (ATE) and automate DFT flows.
• Drive scan implementation and verification across fault models.
• Manage GLS verification, tape-out signoff, pattern delivery, and post-silicon bring-up and debug.

Skills

DFT expertise

Scripting: Python/Perl

Education

Bachelor's degree in EE or related field

Master’s/PhD preferred

Tools

Tessent

Genus

Fusion Compiler

Simvision

Spyglass-DFT

IJTAG tools

Job description

Senior ASIC DFT Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
• 8 years of experience with Design for Test (DFT).
• Experience with DFT EDA Tools (e.g., Tessent, Genus, Fusion Compiler, Simvision).
• Experience with one or more of the following: Scan insertion, Automatic Test Pattern Generation (ATPG), Gate Level Simulations and Silicon Debug, Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), and Internal Joint Test Action Group (IJTAG) tools and flow.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, or a related field.
• Experience working on DFT for complex subsystems with multiple physical partitions, understanding end-to-end SOC flows (Design, Verification, DFT, PD).
• Knowledge of high-performance DFT techniques like SSN and HighBandwidth IJTAG, scaling DFT with minimal area overhead.
• Proficiency with Spyglass-DFT, DFT Scan constraints, evaluating STA paths, and IJTAG (ICL, PDL extraction, and modeling with Siemens Tessent).
• Proficiency in coverage analysis, Gate-Level Simulation (GLS) debug, and silicon debug.
• Proficient with a scripting language such as Perl or Python.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You\'ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will work on SoCs across all aspects of Design for Test (DFT), starting from DFT architecture up until the silicon debug.

Google\'s mission is to organize the world\'s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people\'s lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google\'s Applicant and Candidate Privacy Policy.

Responsibilities

• Work with multi-disciplined and multi-site teams of DFT engineers, RTL, Physical Designer Engineers, SOC DFT and Product Engineering.
• Work on subsystem level DFT SCAN, Memory Built-In Self-Test (MBIST) Architecture with multiple voltage, power domains.
• Develop tests that can be used for production in the automated test equipment (ATE) flow, and write basic to complex scripts to automate the DFT flow.
• Drive scan implementation and verification, ensuring coverage across all fault models.
• Manage Gate-Level Simulation (GLS) verification, tape-out (TO) signoff, pattern delivery, and post-silicon bring-up and debug.

Google is an equal opportunity employer. We are committed to building a diverse and inclusive workforce. See Google\'s EEO Policy and related notices for details.