Senior ASIC DFT Architect — SoC Debug & Validation

SAPSOL Technologies Inc.; United States; On-site; USD 180,000 - 250,000; Full time

Job summary

SAPSOL Technologies Inc. is seeking a Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs.

The role demands deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation. The ideal candidate will have hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools, and a proven ability to lead cross-functional debug efforts to resolve critical

Qualifications

• Strong hands-on experience with ASIC DFT end-to-end ownership.

Responsibilities

• Architect, implement, verify and debug advanced DFT solutions for complex ASIC/SoC designs.
• Lead cross-functional debug efforts and drive resolution of silicon issues.
• Provide deep DFT expertise across architecture, scan insertion, ATPG, MBIST/LBIST, JTAG and boundary scan.

Skills

DFT architecture

ATPG

MBIST/LBIST

JTAG boundary scan

EDA tools

RTL design

Physical design

SoC debug

Issue diagnosis

Communication

Tools

Synopsys

Cadence

Mentor Graphics

Job description

SAPSOL Technologies Inc. is seeking a Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs.

The role demands deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation. The ideal candidate will have hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools, and a proven ability to lead cross-functional debug efforts to resolve critical