Lead ASIC DFT Architect

Sapsol Technologies Inc; United States; Remote; USD 180,000 - 240,000; Full time

Job summary

Sapsol Technologies Inc is seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASICs and SoCs. You will own DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation.

The ideal candidate will lead cross-functional debug efforts, drive fault coverage closure, and mentor junior engineers while developing automation scripts in TCL, Perl or Python to improve flow efficiency and

Qualifications

• Hands-on DFT with end-to-end ownership and requirement-driven qualification.
• Deep understanding of scan architecture, ATPG, MBIST/LBIST, and silicon debug.
• Experience with DFT constraints, timing checks, and design-for-debug methodologies.

Responsibilities

• Lead DFT architecture, implementation, verification, and sign-off for ASIC/SoC designs.
• Drive scan insertion, scan chain stitching, and scan compression workflows.
• Own MBIST/LBIST integration, verification, and debug across bring-up phases.
• Perform DFT debug, fault analysis, root-cause investigation, and coverage closure.
• Develop and validate DFT constraints and timing analysis scripts.
• Collaborate with RTL, physical design, STA, and silicon validation teams.
• Support ATPG pattern generation, simulations, DRC analysis, and diagnosis.
• Mentor junior engineers and drive DFT automation through TCL/Python scripts.

Skills

ASIC DFT ownership

ATPG

MBIST

LBIST

JTAG

EDA tools

Scripting (TCL/Perl/Python)

RTL collaboration

Tools

Synopsys

Cadence

Mentor/Sierra (Siemens)

Tessent

Job description

Sapsol Technologies Inc is seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASICs and SoCs. You will own DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation.

The ideal candidate will lead cross-functional debug efforts, drive fault coverage closure, and mentor junior engineers while developing automation scripts in TCL, Perl or Python to improve flow efficiency and