Senior ASIC DFT Architect - Lead, Debug (Remote)

Best NanoTech; United States; À distance; USD 170 000 - 210 000; Plein temps

Résumé du poste

Best NanoTech is seeking a Lead ASIC DFT Staff Engineer to own DFT architecture, implementation, verification, timing simulation, and debug for complex ASIC and SoC designs. The role requires hands-on expertise in Scan, ATPG, MBIST, DFT timing simulations, SDF/SDC, pattern retargeting, and post-silicon validation.

The engineer will collaborate with RTL, verification, physical design, STA, and silicon validation teams to achieve sign-off and successful silicon bring-up.

Qualifications

• 10+ years of hands-on ASIC/SoC Design-for-Test (DFT).
• End-to-end ownership of DFT implementation on complex ASIC/SoC designs.
• Strong understanding of DFT fundamentals, fault models, test coverage, ATPG, diagnosis, and manufacturing test concepts.

Responsabilités

• Lead end-to-end DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
• Own scan architecture, scan insertion, scan chain stitching, and scan compression implementation.
• Develop and execute ATPG flows, including pattern generation, fault simulation, coverage analysis, and pattern validation.

Connaissances

Scan architecture

ATPG

MBIST

LBIST

DFT timing

SDF/SDC

Pattern retargeting

DFT analysis

DFT debug

Post-silicon validation

TCL scripting

Outils

Synopsys DFTMAX

TetraMAX

Mentor tools

Cadence tools

Description du poste

Best NanoTech is seeking a Lead ASIC DFT Staff Engineer to own DFT architecture, implementation, verification, timing simulation, and debug for complex ASIC and SoC designs. The role requires hands-on expertise in Scan, ATPG, MBIST, DFT timing simulations, SDF/SDC, pattern retargeting, and post-silicon validation.

The engineer will collaborate with RTL, verification, physical design, STA, and silicon validation teams to achieve sign-off and successful silicon bring-up.