Senior ASIC DFT Architect & Debug Lead

Vertogic; United States; Remote; USD 83,000 - 110,000; Full time

Job summary

Vertogic is seeking a Lead ASIC DFT Staff Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC/SoC designs. The role requires ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation.

The ideal candidate will guide cross-functional teams and drive robust testability, high coverage, and efficient debug, leveraging emerging DFT methodologies to improve yield and reliability.

Qualifications

• 10+ years hands-on ASIC DFT experience.
• Deep knowledge of scan architecture, ATPG, MBIST/LBIST.
• Experience with JTAG, boundary scan, and post-silicon debug.
• Proficiency with Synopsys, Cadence, and Mentor EDA tools.
• Strong communication and independent work skills.

Responsibilities

• Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
• Drive scan insertion, scan chain stitching, and scan compression workflows for high coverage.
• Own MBIST/LBIST integration across bring-up phases.
• Perform DFT debug, failure analysis, root-cause investigations, and fault coverage closure.
• Develop DFT constraints including DFT SDC and timing checks.
• Collaborate with RTL, verification, physical design, STA, and silicon validation teams.
• Mentor junior engineers and develop automation scripts (TCL/PERL/Python).

Skills

ASIC DFT

ATPG

MBIST

LBIST

JTAG

Boundary Scan

DFT Fundamentals

Test Coverage

Diagnosis/Debug

Scripting (TCL/PERL/Python)

Tools

Synopsys

Cadence

Mentor EDA

Tessent/SSN

Job description

Vertogic is seeking a Lead ASIC DFT Staff Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC/SoC designs. The role requires ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation.

The ideal candidate will guide cross-functional teams and drive robust testability, high coverage, and efficient debug, leveraging emerging DFT methodologies to improve yield and reliability.