Senior ASIC DFT Architect - Hybrid Work & SoC IP

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 196,000 - 311,000; Full time

Benefits offered by this job

Equity

Job summary

NVIDIA is seeking a Senior ASIC Design Engineer to join the DFT team in Santa Clara. You will own fuse controller and DFT IP design for cutting-edge SoCs, while advancing scalable DFT methods and collaborating across architecture, design, and verification groups.

You will partner with multiple teams to define features, validate through test plans, and support post-silicon bring-up. A strong Verilog background and UVM familiarity are valued assets.

Qualifications

• BS/MS Electrical or Computer Engineering or equivalent with DFT experience.
• 8+ years in SoC architecture, RTL design, and verification.
• Strong Verilog skills; UVM experience is a plus.
• Experience in DFT design, methods and implementation.
• Familiar with clocking, STA, PNR and power optimization.

Responsibilities

• Own the architecture and design of fuse controller and DFT IPs for advanced SoCs.
• Develop, deploy, and enhance DFT methodologies for scalability.
• Collaborate with architects, platform, and software teams on features.
• Work with design, verification, synthesis, timing and backend teams.
• Create test plans for functional and DFT full-chip verification.
• Support post-silicon bring-up and issue resolution; mentor juniors.

Skills

SoC architecture

RTL design

Verilog

Scripting (Python/Perl/Tcl)

Communication

Education

BS/MS Electrical or Computer Engineering

Tools

UVM

Job description

NVIDIA is seeking a Senior ASIC Design Engineer to join the DFT team in Santa Clara. You will own fuse controller and DFT IP design for cutting-edge SoCs, while advancing scalable DFT methods and collaborating across architecture, design, and verification groups.

You will partner with multiple teams to define features, validate through test plans, and support post-silicon bring-up. A strong Verilog background and UVM familiarity are valued assets.