ASIC Design Verification Engineer

Anysilicon; Irvine (CA); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Broadcom is seeking an experienced silicon design engineer to develop high-speed data-center Ethernet silicon for AI and cloud workloads. You will collaborate with global teams across RTL, verification, timing, and silicon validation to deliver world-class devices.

Lead efforts across multiple generations, applying strong ASIC design expertise and knowledge of Ethernet/PCIe. Proficiency in Python or Perl is essential for scripting and automation.

Qualifications

• BSEE with 8 years of industry experience in high-speed communication chip architecture and RTL design
• MSEE with 6 years of experience in high-speed communication chip architecture and RTL design
• Hands-on experience in the ASIC design process required
• Strong knowledge of Ethernet controllers or PCIe desirable

Responsibilities

• Conceive and develop leadership silicon technology for data centers and cloud operators
• Collaborate with a global design and architecture team to create world-class devices
• Front-end design responsibilities include architecture definition, RTL coding, simulation, verification, synthesis, timing closure, and silicon validation
• Provide technical leadership and contribute to evolving designs across multiple generations

Skills

Communication

Documentation

Python

Perl

Team collaboration

Self-starter

Education

BSEE with 8 years experience in high-speed chip architecture

MSEE with 6 years experience

Job description

Join our innovative team at Broadcom, where you'll develop cutting-edge silicon technology for data centers and cloud operators, focusing on high throughput Ethernet products that enhance AI and cloud performance. This role offers a unique opportunity to contribute to the next generation of devices in a dynamic market.

Responsibilities:

• Conceive and develop leadership silicon technology for data centers and cloud operators.
• Collaborate with a global design and architecture team to create world-class devices.
• Engage in all aspects of front-end design, including architecture definition, RTL coding, simulation, verification, synthesis, timing closure, and silicon validation.
• Provide technical leadership and contribute to evolving designs over multiple generations.

Qualifications:

• BSEE with 8 years of industry experience in high-speed communication chip architecture and RTL design, or MSEE with 6 years of experience.
• Strong knowledge of Ethernet controllers or PCIe is highly desired.
• Hands-on experience in the ASIC design process is required.

Skills:

• Strong communication and documentation skills.
• Scripting skills in Python or Perl.
• Self-starter with strong team collaboration abilities.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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