Senior ASIC Design & Timing Engineer

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 179,000 - 332,000; Full time

Job summary

Cadence Design Systems, Inc. in San Jose, CA, is seeking a Product Engineer to collaborate with R&D, Application Engineering, and product marketing to advance chip design software tools. You will provide place-and-route expertise to customers and internal teams, driving RTL-to-GDSII flow improvements.

The role requires seven years of digital implementation experience, strong VLSI timing knowledge, and proficiency with 7nm nodes and EDA tools. Excellent communication is essential.

Qualifications

• BS in Electrical Engineering with at least seven years of digital implementation experience.
• Strong understanding of VLSI physical design and timing analysis.
• Experience with 7nm and below nodes using industry-standard EDA tools.
• Proficiency in scripting languages or AI tools for productivity.
• Excellent verbal and written communication skills.

Responsibilities

• Support Cadence’s digital products and resolve customer issues with R&D and release teams.
• Conduct design benchmarks.
• Develop innovative flows and methodologies tailored to customer needs.

Skills

VLSI design

Timing analysis

EDA tools

Scripting/AI tools

Communication skills

Education

BS in Electrical Engineering

7+ years digital implementation experience

Tools

Synthesis tools

Physical design tools

Signoff tools

Clock tree synthesis

Job description

Cadence Design Systems, Inc. in San Jose, CA, is seeking a Product Engineer to collaborate with R&D, Application Engineering, and product marketing to advance chip design software tools. You will provide place-and-route expertise to customers and internal teams, driving RTL-to-GDSII flow improvements.

The role requires seven years of digital implementation experience, strong VLSI timing knowledge, and proficiency with 7nm nodes and EDA tools. Excellent communication is essential.